Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-15
2004-03-16
Ghyka, Alexander (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S309000
Reexamination Certificate
active
06707086
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for forming crystalline silicon nitride dielectric layers for semiconductor devices.
2. Description of the Related Art
Silicon nitride is used extensively in microelectronic technology for its superior dielectric properties. Typically, silicon nitride includes superior dielectric constant (e.g., ∈=7.5 for silicon nitride) as compared to silicon dioxide (e.g., ∈=3.9). The need for higher capacitance with shrinking dimensions in semiconductor devices such as dynamic random access memories (DRAMs) has been met by reducing the thickness of dielectric layers. Much of the silicon nitride employed for microelectronic applications is deposited by Chemical Vapor Deposition (CVD) techniques and is amorphous in structure. Although thick amorphous silicon nitride (Si
3
N
4
) films have adequately low leakage currents, for thin (<50 Å) dielectric films, higher leakage currents impede, if not preclude, successful device implementation.
To overcome the limitations posed by excessive leakage currents observed in thin CVD nitride dielectric layers, a thermally grown Si
3
N
4
component is added to the CVD nitride layer. Thermally grown Si
3
N
4
is denser than CVD silicon nitride and exhibits superior electrical properties for the same thickness. However, thermal growth of silicon nitride is a self limiting process (at about 950° C. approximate thickness of nitride layer is 18-23 Å which is limited by the thermal growth process). To meet the total required thickness, a CVD nitride layer may be added to the initial thermal nitride.
For DRAM chips employing deep trench capacitors, a node dielectric is deposited in a deep trench. The node dielectric separates the storage node in the deep trench from a buried plate outside the trench to form a capacitor. It is desirable for the node dielectric to be as thin as possible to provide a high capacitance with minimal or low leakage. Node dielectrics have evolved from using an oxide only (O) dielectric layer to a mixed oxide-nitride (ONO) and currently to nitride-oxide (NO) dielectric layers to take advantage of the higher ∈ of Si
3
N
4
. Similarly, for gate dielectrics, in addition to a reduction in thickness, incorporation of some nitride into the oxide film is being explored to boost the physical thickness (and dielectric constant) while keeping the equivalent oxide thickness small enough to meet the needs of smaller and faster devices.
A desirable option for improving the properties of ultra-thin dielectric layers would be to employ crystalline Si
3
N
4
films for such applications. Unlike CVD nitride films, in which the large leakage currents have been attributed to the presence of a large number of defects and pinholes, crystalline nitride films by nature could be denser and relatively defect free. However, crystalline Si
3
N
4
films are difficult to grow and unstable due to lattice mismatch with silicon and the consequent excessive strain at the growth interface. An added complication for the case of a node dielectric is the presence of a thin non-stoichiometric native oxide on the exposed silicon surface of a substrate which inhibits the reaction between nitridizing species and the silicon substrate. This native oxide may be partially responsible for the electrical leakage in thermally grown nitride films.
Therefore, a need exists for a method to preclean and remove a native oxide before thermal nitridation of exposed silicon is performed. A further need exists for a method for forming a crystalline silicon nitride for semiconductor devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed silicon surface, precleaning the exposed surface by annealing in a hydrogen ambient and further annealing or exposing the exposed surface to nitrogen (e.g. in an ammonia ambient) to form a crystalline silicon nitride layer.
A method for forming a node dielectric layer in deep trenches, includes the steps of providing a crystalline silicon substrate with trenches formed therein, the trenches including surfaces with exposed silicon, precleaning the exposed silicon surfaces by employing a hydrogen prebake, exposing the exposed surfaces to ammonia to form a crystalline silicon nitride layer, depositing an amorphous silicon nitride layer over the crystalline silicon nitride layer, and oxidizing the amorphous silicon nitride layer to form a node (NO) dielectric layer.
In alternate methods, the step of precleaning may include the step of employing a wet cleaning process to remove native oxide from the exposed surface(s). The cleaning process may include HF cleaning. The step of precleaning may include the step of prebaking the exposed surface(s), in situ, in the presence of hydrogen gas, hydrogen plasma or similar reducing atmospheres at a temperature between about 400° C. and about 1300° C. at a pressure between about 10
−9
Torr and about 600 Torr. The step of precleaning may include the step of prebaking the exposed surface(s) in the presence of hydrogen gas introduced at a flow rate of between about 100 sccm and about 20 SLM for between about 2 seconds and about 3600 seconds. Flow rates and time durations can vary over a wide range of acceptable values depending on the conditions and the tool set employed. The step of annealing/exposing the exposed surface(s) to nitrogen to form a crystalline silicon nitride layer may include the step of introducing ammonia at a temperature of between about 400° C. and about 1300° C. The step of exposing the exposed surface(s) to nitrogen to form a crystalline silicon nitride layer may include the step of maintaining ammonia at a pressure of between about 10
−6
Torr and about one atmosphere or greater. A semiconductor device may be fabricated in accordance with the methods described herein.
A trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surfaces substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the surfaces of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.
In alternate embodiments, the crystalline silicon nitride layer may include a thickness of between about 3 Å and about 40 Å. The dielectric stack may include an oxidized amorphous nitride layer.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5643823 (1997-07-01), Ho et al.
patent: 6100132 (2000-08-01), Sato et al.
patent: 6194754 (2001-02-01), Aggarval et al.
patent: 6495876 (2002-12-01), Bronner et al.
patent: 2002/0137362 (2002-09-01), Jammy et al.
patent: 0684637 (1995-05-01), None
Batson Philip E.
Flaitz Philip L.
Jammy Rajarao
Shen Hua
Wang Yun Yu
Ghyka Alexander
Infineon - Technologies AG
LandOfFree
Method for forming crystalline silicon nitride does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming crystalline silicon nitride, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming crystalline silicon nitride will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3228456