Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-10-18
1999-10-19
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438632, 438633, 438637, 438643, 438644, 438645, 438656, 438672, H01L 21311, H01L 21461
Patent
active
059703741
ABSTRACT:
A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier materials are deposited into contact or via openings by physical-vapor-deposition (PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in the formations of cusps along the walls at the mouth of the opening. These cusps obstruct the material stream into the depth of the opening, resulting in inadequate coverage at the base of the opening particularly at the corners. This increases the chance of failure of the barrier material resulting in a reliability exposure. In addition, the cusps, if not removed, cause the formation of voids in subsequently deposited conductive plugs. The invention teaches the insulative layer, wherein the openings are formed, to be deposited to a greater thickness than required by the design. The openings are then formed and filled with a spin-on-glass. The insulative layer is then polished to the design thickness, removing the cusps. The spin-on-glass, which protects the openings from damage and contamination during polishing, is removed and an adhesion layer is applied prior to the deposition of the conductive material of the contact or via.
REFERENCES:
patent: 4960732 (1990-10-01), Dixit et al.
patent: 5387550 (1995-02-01), Cheffings et al.
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5420070 (1995-05-01), Matsuura et al.
patent: 5462895 (1995-10-01), Chen
patent: 5470792 (1995-11-01), Yamada
patent: 5516729 (1996-05-01), Dawson et al.
patent: 5654234 (1997-08-01), Shih et al.
patent: 5658829 (1997-08-01), Matthews et al.
patent: 5698467 (1997-12-01), Sakao et al.
patent: 5739047 (1998-04-01), Chiang
patent: 5747382 (1998-05-01), Huang et al.
S. Wolf et al, "Silicon Processing For The VLSI Era" Lattice Press, Sunset Beach, CA, p. 368.
Chartered Semiconductor Manufacturing Ltd.
Nguyen Ha Tran
Niebling John F.
Pike Rosemary L. S.
Saile George O.
LandOfFree
Method for forming contacts and vias with improved barrier metal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming contacts and vias with improved barrier metal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming contacts and vias with improved barrier metal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2068717