Method for forming contact plug of semiconductor device

Details Method for forming contact plug of semiconductor device Method for forming contact plug of semiconductor device

2002-12-31

2004-04-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S692000, C257SE21168

Reexamination Certificate

active

06723640

ABSTRACT:

This nonprovisional application claims priority under 35 U.S.C. Å119(a) on Patent Application No. 2000-37255 and 2000-42341 filed in Republic of Korea on Jun. 29, 2002 and Jul. 19, 2002, respectively, which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for forming a contact plug of a semiconductor device capable of reducing step coverage between a highly dense pattern area, i.e., a cell area and a lowly dense pattern area, i.e., a peripheral circuit area.
2. Description of Related Arts
As integration of a semiconductor device has been augmented progressively, a vertical array structure is applied to a unit device. Particularly, a technique for forming a contact plug is adapted and applied to make an electric connection between the unit devices. Currently, this technique for forming a contact plug has been generalized in a semiconductor device fabrication process.
During the contact plug formation, it is necessary to apply a planarization process such as a chemical mechanical polishing (hereinafter referred as to CMP) process or an etchback process in order to isolate contact plugs.
In addition, there inevitably occurs a step difference between insulating layers in a highly dense pattern area and a lowly dense pattern area, i.e., a cell area and a peripheral circuit area, respectively. Therefore, it is necessary to perform sufficiently a flow process which accompanies a high temperature process in order to reduce the step difference.
However, the high temperature process is hardly applicable because it causes properties of a sub-device such as a gate electrode, a junction between a source and a drain and so forth to be degraded. For instance, leakage currents increase due to a decrease in a gate voltage. Although it is attempted to use a flowable dielectric material having an excellent properties of planarization and gap-fill, there results in a problem of micro-pores produced at a bottom structure during the gap-fill procedure. For this reason, this attempt has also a difficulty in applying to a semiconductor device fabrication process.
FIGS. 1A
to
1
C are cross-sectional views showing a process for forming a contact plug of a semiconductor device according to a prior art.
Particularly,
FIG. 1A
illustrates a state in that a number of gate electrode patterns are formed in a cell area and a peripheral circuit area. The following will describe procedures for a contact plug formation process in detail.
A semiconductor substrate
10
wherein various elements for fabricating a semiconductor device are prepared is divided into a cell area and a peripheral circuit area. On the substrate
10
, a field oxide layer (not shown) is formed to classify an activation area and a device separation area through a local oxidation of silicon (hereinafter referred as to LOCOS) process or a shallow trench isolation (hereinafter referred as to STI) process.
A number of conductive patterns neighboring upon the activation area, e.g., a number of gate electrode patterns, are formed. That is, an oxide layer based gate insulating layer
11
is deposited, and a gate electrode
12
is formed thereon by depositing a single or combinations of a metal layer using tungsten, a metal nitride layer using a tungsten nitride layer and a metal silicide such as tungsten silicide or polysilicon. After the formation of the gate electrode
12
, an insulating layer to be used for a nitride layer based hard mask is deposited.
Subsequently, a photoresist pattern (not shown) for forming the gate electrode pattern is formed. Afterwards, the insulating layer to be used for the hard mask, the gate electrode material and the gate oxide layer are selectively etched by using the gate electrode pattern as an etching mask so as to form the gate electrode pattern in a stack structure including the gate oxide layer based insulating layer
11
, the gate electrode
12
and the hard mask
13
.
Along an overall profile wherein the gate electrode pattern is formed, a nitride layer based insulating layer
14
to be used for a spacer is thinly deposited. Herein, the reason for using the nitride based material is to provide an etching selection ratio with the oxide layer during a self align contact (hereinafter referred as to SAC) process for forming a contact plug and to prevent losses of the gate electrode pattern when performing the etching process.
In continuous to the deposition of the nitride layer based insulating layer
14
, a boro phospho silicate glass (BPSG) layer is deposited to form another insulating layer
15
for insulating an inter-layer by sufficiently covering the gate electrode pattern and an upper part of the substrate
10
. Meanwhile, since the peripheral circuit area has a lower vertical height than the cell area because of a difference in densities of patterns in the cell area and the peripheral circuit area, there results in a step difference between the two areas as denoted X in FIG.
1
A.
Next, a cell contact open mask (not shown) for forming a contact plug or a contact pad for electrically connecting devices, which will be formed on the upper structure through a subsequent process, is formed on the substrate
10
between the gate electrode patterns, more particularly, a junction between a source and a drain within the substrate
10
. Then, the insulating layer
15
is selectively etched by using the cell contact open mask as an etching mask so as to form a contact hole for opening a surface of the substrate
10
between the gate electrode patterns. A conductive material, e.g., polysilicon doped with impurities is deposited as sufficient as to contact to the opened surface of the substrate
10
and fill the contact hole so that a contact plug
16
is formed in the end.
FIG. 1B
is a cross-sectional view illustrating the above process.
An etchback process or a CMP process is instigated to planarize the contact plug
16
and the insulating layer
15
for isolating each contact plug
16
formed.
At this time, it is also possible to planarize the above with the hard mask
13
or a portion of the insulating layer
15
higher than the hard mask
13
.
In the mean time, the described insulating layer
15
mainly uses the BPSG layer. However, during the CMP process, the BPSG layer has a higher removal rate than the polysilicon, which is used for the contact plug
16
, and this factor results in a difficulty in controlling the removal during the etching process. Also, in case of applying the planarization process by taking the cell area as a basis for an etching target until exposing a surface of the hard mask
13
, e.g., the CMP process for isolating each contact plug
16
, there results in an attack to the gate electrode pattern in the peripheral circuit area. This case is expressed as ‘A’ in
FIG. 1C
, which is a cross-sectional view showing the loss of the hard mask
13
.
FIG. 2
is a scanning electron microscopy (SEM) picture illustrating a contact plug of a semiconductor device fabricated in accordance with the method.
In case of proceeding the planarization process by taking the peripheral circuit area as a basis for an etching target in order to block the attack to the gate electrode pattern in the peripheral circuit area, it is, however, impossible to isolate each plug
16
.
Consequently, it is urgently required to develop a special technology for solving the problems in that the BPSG based insulating layer has a higher removal rate than the polysilicon and the attack to the gate electrode patterns caused by the step difference between the cell and the peripheral circuit areas.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for forming a contact plug of a semiconductor device suitable for blocking an attack to sub-structures such as conductive patterns, caused by an unequal etching rate of an insulating layer and a step difference between a highly dense pattern area and a lowly dense pattern area.
In accordance with an asp

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