Method for forming conductive lines and stacked vias

Details Method for forming conductive lines and stacked vias Method for forming conductive lines and stacked vias

1995-09-05

1998-05-05

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438656, 438672, 438720, H01L 21441

Patent

active

057473838

ABSTRACT:
A method for fabricating an improved connection between active device regions in silicon, to overlying metallization levels, has been developed. A LPCVD tungsten contact plug process, which results in optimum coplanarity between the top surface of the tungsten plug and the surrounding insulator surface, has been created.

REFERENCES:
patent: 4398338 (1983-08-01), Tickle et al.
patent: 4592802 (1986-06-01), Deleonibus et al.
patent: 5010039 (1991-04-01), Ku et al.
patent: 5024722 (1991-06-01), Cathey, Jr.
patent: 5231051 (1993-07-01), Baldi et al.
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5286677 (1994-02-01), Wu
patent: 5407698 (1995-04-01), Emesh

Affiliated with

Also associated with

Rating

Method for forming conductive lines and stacked vias does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming conductive lines and stacked vias, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming conductive lines and stacked vias will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-53921