Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-19
2003-06-24
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S627000, C438S706000, C438S786000
Reexamination Certificate
active
06583054
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for forming conductive lines in a semiconductor device in which a trench for forming the upper conductive line is overlapped with contact holes for exposing the lower conductive line, the trench being filled with a conductive metal to form the upper conductive line.
2. Discussion of Related Art
As a material for the conductive lines in a semiconductor device, there has been widely used aluminum or aluminum alloy film which are easy to provide formation of pattern through dry etch and relatively inexpensive with high electrical conductivity and good adhesiveness with silicon oxide layers. With larger integration of semiconductor devices, however, cells decrease in size and the conductive lines have a fine width and multilevel structure, so that deterioration of topography may be caused in the surface to form conductive lines, or step coverage becomes more significant in a curved portion such as interior part of contact holes. It means, when a conductive film is formed by sputtering aluminum or aluminum alloy to provide a conductive line, the curved portion of the conductive film is locally made thinner due to shadow effect, which is appeared severe in a contact hole that has the aspect ratio greater than unity.
Therefore, many studies have been made on another deposition techniques in place of the conventional physical deposition such as sputtering, in order to improve step coverage by depositing aluminum or aluminum alloy through chemical vapor deposition (hereinafter called CVD) that may be used to planarize the surface of a layer to be formed.
However, as the conductive line becomes extremely fine with larger integration of semiconductor devices, it is required to form the conductive line consisting of copper (Cu), gold (Au) or silver (Ag) that has higher electrical conductivity compared to aluminum or aluminum alloy. Those metals such as Cu, Au and Ag can enhance reliability of the device because they exhibit good electron migration and stress migration characteristics as well as low resistivity relative to aluminum. However, a use of halogen compounds in patterning Cu, Au or Ag to form a conductive line as conventionally used in etching aluminum involves a low etch rate owing to low vapor pressure of the halogen compounds reacted with Cu, Au or Ag. It is thus needed to raise the temperature up to about 500° C. in order to increase the vapor pressure and enhance the etch rate in etching Cu, Au or Ag with halogen compounds.
Instead of forming conductive lines consisting of Cu, Au or Ag through etch for patterning, there has been developed ‘Dual Damascene’ technology in which a trench is formed in the substrate and Cu, Au or Ag is then deposited therein, followed by chemical mechanical polishing (hereinafter called CMP) in such a manner that conductive lines are buried in the trench.
FIGS. 1A
to
1
D are cross-sectional views for illustrating a process for forming conductive lines in a semiconductor device according to a related art.
Referring to
FIG. 1A
, a first conductive line
13
is formed at a predetermined portion on a substrate
11
. On the substrate
11
is deposited silicon oxide or silicon nitride by chemical vapor deposition (hereinafter called CVD) so as to cover the first conductive line
13
, thereby forming an insulating layer
15
. The substrate
11
may be an insulating layer formed on a semiconductor substrate having transistors or lower conductive lines.
Referring to
FIG. 1B
, the insulating layer
15
is coated with photoresist. A first photo resist pattern
17
, which exposes a portion that corresponds to a predetermined portion of the first conductive line
13
of the insulating layer
15
, is formed by exposure and development to be patterned.
With the first photo resist pattern
17
used as a mask, the exposed portion of the insulating layer
15
is etched a predetermined depth by an anisotropic etching such as reactive ion etching (hereinafter called RIE) to form a first opening
19
.
Referring to
FIG. 1C
, the first photo resist pattern
17
is removed to expose the insulating layer
15
. The insulating layer
15
is coated with photoresist. A second photo resist pattern
21
, which exposes a portion that corresponds to a predetermined portion inclusive of the first opening
19
of the insulating layer
15
, is formed by exposure and development to be patterned in a strip shape (not shown).
With the second photo resist pattern
21
used as a mask, the exposed part of the insulating layer
15
undergoes an anisotropic etching such as RIE, forming a second opening
23
in the form of a trench. At this stage, the bottom surface of the first opening
19
is also etched such that the opening
19
extends to expose the first conductive line
13
. So, the first opening
19
forms a contact hole.
Referring to
FIG. 1D
, the second photo resist pattern
21
is removed and a barrier metal layer
27
being formed on the insulating layer
15
including the surfaces of the first and second openings
19
and
23
by a sputtering method. On the barrier metal layer
27
is then deposited a conductive metal by CVD to fill the first and second openings
19
and
23
.
The conductive metal and the barrier metal layer
27
are subjected by CMP so as to expose the insulating layer
15
that they remain only in the first and second openings
19
and
23
. The conductive metal remaining within the first and second openings
19
and
23
forms a second conductive line
29
.
The related art method for forming conductive lines in a semiconductor device as described above, however, presents a problem in that the first insulating layer has a difference in thickness between the portion in which the first opening is formed and the rest having no opening formed therein, causing distortion of the pattern due to halation during an exposure upon the second photo resist pattern. Additionally, the photo resist pattern charged in the first opening is difficult to remove when patterning the second photo resist, so that an increase in the contact resistance may occur since the area of the fist conductive line exposed through the first opening extended in formation of the second opening becomes reduced.
SUMMARY OF THE INVENTION
Accordingly, an objective of the present invention is to provide a method for forming conductive lines in a semiconductor device in which halation is avoidable when patterning a second photo resist to form a second opening, thereby enhancing reliability of the device.
Another objective of the present invention is to provide a method for forming conductive lines in a semiconductor device, in which a decrease in the exposed area of a first conductive line due to extension of a first opening is avoided, and thereby, contact resistance is not increased.
To achieve the first object of the present invention, a semiconductor device includes: a method for forming conductive lines in a semiconductor device includes the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer on the first conductive line to form a first opening; (d) forming a second insulating layer on the first insulating layer to be in contact with the upper part of the first opening, thereby sealing the first opening; (e) etching the first and second insulating layers corresponding to the first conductive line to form a second opening and at the same time extend the first opening so as to expose the first conductive line; and (f) forming a second conductive line within the first and second openings so as to be connected with the first conductive line.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5407870 (1995-0
Hyundai Microelectronics Co., Ltd.
Morgan & Lewis & Bockius, LLP
Nguyen Ha Tran
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