Method for forming conductive line

Details Method for forming conductive line Method for forming conductive line

1999-05-17

2001-03-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S631000

Reexamination Certificate

active

06197680

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88101058, filed Jan. 25, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a conductive layer.
2. Description of Related Art
As a line width of a semiconductor device is gradually minimized, the distance between two neighboring conductive lines is gradually reduced. However, the shorter the distance between the two neighboring conductive lines is, the more serious a parasitic capacitor effect is. A parasitic capacitor is generated between the two neighboring conductive lines. A parasitic capacitor effect is affected by a dielectric constant of the dielectric layer and a distance between the two neighboring conductive lines. Consequently, a high dielectric constant and a small distance between the two neighboring conductive lines both easily cause a parasitic capacitor. When the parasitic capacitor effect is serious, resistance capacitance (RC) time delay is increased so as to decrease transferring speed in integrated circuits.
FIG. 1
is a schematic, cross-sectional view of a conductive line.
Referring to
FIG. 1
, a metallic layer (not shown) is formed on a semiconductor substrate
100
. A photoresist layer (not shown) having a pattern of a subsequently formed metal line is formed on the metallic layer. Two etching steps are performed on the metallic layer. Using the photoresist layer as a mask, a first etching step is performed on the metallic layer to form a metal line
102
. A second etching step is performed on the metal line
102
to clean away residue generated on the substrate
100
during the first etching step. A dielectric layer
104
is formed over the substrate
100
to cover the metal line
102
. An air gap
106
is commonly formed in the dielectric layer
104
between the two neighboring metal lines
102
. A dielectric layer
104
a
including the air gap
106
and the dielectric layer
104
is formed. Since the air gap
106
exists in the dielectric layer
104
, the dielectric constant of the dielectric layer
104
a
can be minimized.
However, the conventionally formed conductive line
102
has a tapered profile, as shown in FIG.
1
. In other words, the conductive line
102
has a wider bottom than the top. Hence, a distance between the two neighboring metal lines is decreased. While forming the dielectric layer
104
on the substrate
100
, the dielectric layer
104
has a better coverage ability because the conductive line
102
has a tapered profile. Consequently, the dielectric layer
104
easily fills an area between the two neighboring metal lines so that the air gap
106
becomes smaller. Thus, the air gap
106
cannot efficiently reduce the dielectric constant of the dielectric layer
104
a
so as to increase a parasitic capacitor induced between the two metal lines
102
.
Moreover, the conventionally formed metal line
102
has a tapered profile so as to decrease a distance between the two neighboring metal lines
102
. Consequently, a parasitic capacitor generated between the two metal lines
102
is also increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an improved method for forming a conductive layer. The method can increase a distance between the two neighboring conductive lines. Moreover, the invention can form a larger air gap than the conventionally formed air gap in the dielectric layer so that the dielectric layer has a lower dielectric constant. Therefore, a parasitic capacitor induced between the conductive lines can be improved.
The invention provides an improved method for forming a conductive layer on a semiconductor substrate. A conductive layer is formed on the substrate. A photolithography step is performed on the conductive layer. A first etching step is performed on the conductive layer to form a plurality of conductive lines. A second etching step is performed on the plurality of the conductive lines to undercut the plurality of the conductive lines so as to make the plurality of the conductive lines have a smaller bottom and to increase a distance between the two neighboring conductive lines. A third etching step is performed to remove a residue produced on the substrate during the first and the second etching steps. A dielectric layer is formed to cover the conductive line. A planarization process is performed on the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5143820 (1992-09-01), Kotecha et al.
patent: 5702564 (1997-12-01), Shen
patent: 5817573 (1998-10-01), Rhodes et al.
patent: 5863707 (1999-01-01), Lin

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