Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
2000-03-17
2001-06-26
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C438S185000, C438S233000, C438S299000, C438S303000, C438S305000, C438S586000, C438S683000, C438S651000, 43, 43, 43
Reexamination Certificate
active
06251711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The proposed invention relates to a method for forming bridge free silicide, and more particularly to a method not only improves quality of salicide but also provides a self-aligned contact process in the self-aligned salicide process.
2. Description of the Prior Art
Silicide is an important field in contemporary semiconductor fabrication. Advantages of silicide comprise lower contact resistance, withstand high temperature and allowable of self-alignment process. Further, silicides usually are formed by reacting refractory or near noble metals with silicon. Among them are titanium silicide (TiSi2), cobalt silicide (CoSi2), tungsten silicide (Wsi2), platinum silicide (Ptsi2), molybdenum silicide (MoSi2), palladium silicide (PdSi2), and tantalum silicide (TaSi2).
However, owing to the fact that a higher temperature annealing is need to carry out those refractory metal silicide, an unavoidable issue is the bridge phenomena that means the silicide on gate is connected to the silicide on source/drain and then an unexpected short is happened. Sequentially, the bridge phenomena can be further illustrated in following paragraphs.
In conventional salicide process, metal is formed on the gate, the sidewall spacers and the source/drain regions. And then one, two or more annealing processes are performed to react the metal with the polysilicon (silicon) of the gate and the silicon (polysilicon) of the source/drain to form silicide. Following these annealing process, an etching process is performed to remove any unreacted metal.
One of principal functions of sidewall spacers is to separate silicide on the gate from silicide on the source/drain. However, despite the incorporation of spacers, silicide also may form laterally and easily bridge the separation between the gate and the source/drain. Then the gate is shorted to the source/drain, and so-called “bridge phenomena” occurs. In addition, silicon (polysilicon) diffuses into the metal that covers the sidewall spacers and subsequently reacts with the metal.
Moreover, some conditions tend to favor lateral silicide formation. For examples, conventional furnace annealing in an inert gas atmosphere may foster rapid lateral silicide formation. On the other hand, processing in the sub-0.25 .mu.m processing, the minimum gate width may approach or even reach the dimensions of the grain boundaries between the individual grains of the gate, and then these grain boundaries act as natural barriers to silicon diffusion. Another possible reason of lateral silicide formation is that diffusion of silicon (polysilicon) is unavoidable and then unexpected silicide may be formed on sidewall spacers. Obviously, when scale is reduced danger of the unexpected silicide is increased.
In summary, it is beyond any doubt that bride phenomena is serious issue in application of silicide, and then a method to overcome the issue is instantly required.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a manufacturable method for forming silicide without bridge phenomena.
Another object of the present invention is to provide a practical silicide scheme that provides a self-aligned contacted process in conventional self-aligned silicide process.
A further object of the present invention is to provide a salicide process that not only overcomes bridging issue but also reserves self-alignment advantage of silicide.
In short, first preferred embodiment is a method comprises following steps: providing a substrate with a pad layer on the substrate; forming a first cap layer on the pad layer; defining a trench region; removing part of the pad layer and part of the first cap layer that are located inside the trench region such that a trench is formed; filling the trench by a gate oxide layer and a polysilicon layer in sequence; capping a first metal layer on the polysilicon layer; performing a first rapid thermal process to form a first silicide layer over the gate oxide layer; removing excess the first metal layer; forming a second cap layer on the first silicide layer; planarizing surface of both the first cap layer and the second cap layer; removing the first cap layer; removing part of the pad layer that is not covered by the gate oxide layer and then a gate structure being formed; forming two light doped drain in the substrate; forming a spacer on sidewall of the gate structure; forming a sources and a drain in the substrate, herein the source and the drain is located around the light doped drains; forming some second metal layers on both the source and the drain; performing a second thermal process to form two second silicide layer over the source and the drain; removing excess the second metal layer; and then forming a third rapid thermal process.
In comparison, another preferred embodiment is a process comprises following steps: providing a substrate that is covered by a first cap layer; forming a trench in the first cap layer; filling the trench by a dielectric layer and a polysilicon layer in sequence; forming a first silicide layer on the dielectric layer; forming a second cap layer on the first silicide layer; removing part of the first cap layer that is outside the trench and then a gate structure being formed; forming a spacer, a source and a drain around the gate structure; forming a second silicide layer on the source and the drain; forming a third cap layer to cover the substrate after second silicide layer is formed; and forming two contacts in the third cap layer, wherein one contact is connected to source and another contact is connected to drain.
REFERENCES:
patent: 4873205 (1989-10-01), Critchlow et al.
patent: 4983544 (1991-01-01), Lu et al.
patent: 5753557 (1998-05-01), Tseng
patent: 5783486 (1998-07-01), Tseng
Fang Edberg
Hsieh Wen-Yi
Tsai Teng-Chun
Elms Richard
Luu Pho
United Microelectronics Corp.
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