Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-27
2004-04-20
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S622000, C438S624000, C438S628000, C438S644000, C438S654000
Reexamination Certificate
active
06723628
ABSTRACT:
Japanese Patent Application No. 2000-086608, filed Mar. 27, 2000, is hereby incorporated by reference in its entirety. U.S. patent application Ser. No. 09/818,743 is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods for manufacturing the same, including semiconductor devices having a characteristic structure of pad sections (external connection electrodes) and methods for manufacturing the same.
RELATED ART
FIG. 4
shows a cross-sectional view of one example of a conventional bonding pad section. In this example, a pad section
130
is formed in a specified region over an uppermost interlayer dielectric layer
120
that is formed from a PBSG. The pad section
130
is formed from a titanium layer
132
, a titanium nitride layer
134
and an aluminum alloy layer
136
. A passivation layer
140
is formed over surfaces of the interlayer dielectric layer
120
and the pad section
130
. An opening section
142
that forms a bonding region is formed in the passivation layer
140
. Wire bonding with, for example, a wire
150
is conducted in the opening section
142
.
The bonding pad structure can be formed in the same steps that are conducted to form the first wiring layer. More particularly, the uppermost interlayer dielectric layer
120
is formed in the same step that is conducted to form a first interlayer dielectric layer. The titanium layer
132
and the titanium nitride layer
134
that compose the pad section
130
are formed in the same steps that are conducted to form a barrier layer formed between an impurity diffusion layer formed in the semiconductor substrate and a contact section formed in the first interlayer dielectric layer. Further, the aluminum alloy layer
136
is formed in the same step that is conducted to form the contact section and the first wiring layer.
PROBLEMS WITH THE RELATED ART
In the bonding pad structure shown in
FIG. 4
, when the bonding wire
150
is bonded to the pad section
130
, an exfoliation may occur near the interface between the pad section
130
and the interlayer dielectric layer
120
. This type of exfoliation is thought to take place because a weak layer such as a titanium oxide layer is formed near the interface between the titanium layer
132
and the interlayer dielectric layer
120
and thus the coherency between the interlayer dielectric layer
120
and the titanium layer
132
lowers.
SUMMARY
One embodiment relates to a semiconductor device including a pad section over an interlayer dielectric layer, wherein the pad section includes a wetting layer and a metal wiring layer. In addition, the metal wiring layer includes an alloy layer that contacts the wetting layer, the alloy layer including a material that forms the wetting layer and a material that forms the metal wiring layer.
Another embodiment relates to a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a interlayer dielectric layer; (b) forming a wetting layer over the interlayer dielectric layer; (c) forming at least a portion of a metal wiring layer over the wetting layer at a temperature of 350° C. or higher, and forming an alloy layer including a material comprising the wetting layer and a material comprising the metal wiring layer; and (d) forming a pad section by patterning the wetting layer and the metal wiring layer.
Another embodiment relates to a method for manufacturing a semiconductor device including a pad section, including providing a interlayer dielectric layer by forming three silicon oxide layers. The method also includes depositing a wetting layer consisting essentially of a first material selected from the group consisting of titanium, cobalt, zirconium, silicon and niobium. A first layer is deposited over the wetting layer, the first layer comprising a second material including aluminum deposited at a temperature of no greater than 200° C. A second layer is deposited over the first layer, the second layer comprising the second material deposited at a temperature of no less than 350° C.
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Notice of Reasons of Rejection for Japanese Patent Application No. 2000-086608 (from which priority is claimed in U.S. Ser. No. 09/817,935), dated Mar. 18, 2003, which lists JP10-233443 and JP59-172745.
Notice of Reasons of Rejection for Japanese Patent Application No. 2000-086607 (from which priority is claimed in U.S. Ser. No. 09/818,743), dated Mar. 18, 2003, which lists JP10-233443, JP07-078821, JP09-092717, JP59-032143, JP03-227540, JP11-145134 and JP2000-100816.
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Notice of Reasons of Rejection for Japanese Patent Application No. 2000-086607 (from which priority is claimed in U.S. Ser. No. 09/818,743), dated Jun. 10, 2003, which lists JP11-145134, JP11-37452, JP11-121458, JP06-005653 and JP2000-188333.
Asahina Michio
Matsumoto Kazuki
Morozumi Yukio
Chen Jack
Konrad Raynes & Victor LLP
Pham Thanhha
Raynes Alan S.
Seiko Epson Corporation
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