Method for forming bit lines for semiconductor devices

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant

Reexamination Certificate

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C257S324000, C257SE21657, C438S288000, C438S519000, C438S545000, C438S555000

Reexamination Certificate

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07972948

ABSTRACT:
A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.

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Co-pending U.S. Appl. No. 12/048,549, filed Mar. 14, 2008 entitled “Method For Forming Bit Lines For Semiconductor Devices” by Weidong Qian et al., 30 pages.

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