Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-28
2002-10-15
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S637000, C438S656000, C438S687000, C438S706000
Reexamination Certificate
active
06465343
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the formation of metal interconnection layers during the manufacture of semiconductor devices, and more particularly to the formation of a backend interconnect using copper and ultra low k material.
BACKGROUND OF THE INVENTION
The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance interconnection pattern, particularly where sub-micron via contacts and trenches have high aspects ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, made from a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacing. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductive substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metalization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric layer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
In prior technologies, aluminum was used in very large scale integration interconnect metalization. Copper and copper alloys have received considerable attention as a candidate for replacing aluminum in these metalizations. Copper has a lower resistivity than aluminum and improved electrical properties compared to tungsten, making copper a desirable metal for use as a conductive plug as well as conductive wiring.
In other efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as a replacement for dielectric materials with higher k values. Lowering the overall k values of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, low k materials, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, etc., are often more difficult to handle than traditionally employed higher k materials, such as an oxide. For example, inorganic low k dielectric materials are readily damaged by techniques used to removed photoresist materials after the patterning of a layer. Hence, a feature formed in an inorganic low k dielectric layer may be damaged when the photoresist layer used to form the trench is removed. Damage to the low k dielectric layer is especially critical in the layers containing conductive lines, and not as critical in layers containing the conductive plugs. This is due to the importance of the line-to-line capacitance being maintained as low as possible to improve the device performance.
There is therefore a need to provide a method for performing a backend interconnect using low k or ultra low k electric materials with copper lines, but without causing the damage to the sidewalls normally created by the photoresist removal process.
SUMMARY OF THE INVENTION
These and other needs are met by embodiments of the present invention which provide a method of forming a metal interconnect structure comprising the steps of etching a conductive layer to form conductive lines with spaces between the lines such that all photoresist material is removed during the etching of the conductive layer. The spaces between the conductive lines are filled with low k dielectric material. A polish layer is then deposited over the low k dielectric material and polished. Via holes are etched through the polish layer into the low k dielectric layer. The via holes are aligned over the conductive lines.
By etching the conductive layer to form conductive lines and spaces between the lines, removing all the photoresist material during this etching process, and subsequently filling the spaces between the conductive lines with low k dielectric material, it can be assured that the low k dielectric material between the conductive lines is not subjected to a photoresist removal process. Hence, the low k dielectric material is not degraded by exposure to the photoresist removal process. In certain embodiments of the invention, the conductive material is copper. In these embodiments, an advantageous method of etching the copper to form the conductive lines with the spaces therebetween is employed. With the spaces formed between the conductive copper lines, the photoresist material may be removed prior to filling the spaces with the low k dielectric material. The sequence of processing steps improves the structural integrity of the low k dielectric layer.
The earlier stated needs are also met by another aspect of the present invention which provides a method of forming a backend interconnect. This method comprises the steps of etching a copper layer to form copper lines with spaces between the copper lines. Low k dielectric material is formed in the spaces and over the copper lines. Via holes are etched in the low k dielectric layer above the copper lines, while preventing the low k dielectric material on the spaces from exposure to photoresist removal processes. The via holes are then filled with copper.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.
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Chaudhuri Olik
Smoot Stephen W.
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