Method for forming an interconnect structure using a CVD...

Details Method for forming an interconnect structure using a CVD... Method for forming an interconnect structure using a CVD...

2002-01-29

2003-10-14

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S072000

Reexamination Certificate

active

06632707

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the formation of metal interconnection layers during the manufacture of semiconductor devices, and more particularly to the prevention of via poisoning during the formation of a trench structure in a low k dielectric material.
BACKGROUND OF THE INVENTION
The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacings. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metalization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising of at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques and filling the opening with conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher-k values. Lowering the overall k values of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, low k materials such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, etc., are often more difficult to handle than traditionally employed higher k materials, such as an oxide. For example, low k dielectric materials are readily damaged by techniques used to remove photoresist materials after the patterning of a layer. Hence, a feature formed in a low k dielectric layer may be damaged when the photoresist mask used to form the feature (e.g., trench or via) is removed.
Other problems that have been observed when working with low k materials is that of via poisoning and resist scumming. For example, via poisoning may be observed after the formation of a via in a low k dielectric layer and the subsequent formation and patterning in the photoresist that forms the trench mask. The via poisoning may cause a mushroom shape of resist to form at the top of the via hole, and resist scum may be seen at the surface of the dielectric layer in the mask opening. An example of this is depicted in
FIG. 1. A
substrate
10
, which may be a conductive material such as copper, is covered by a bottom etch-stop layer
12
, which can be made of silicon nitride, for example. The low k dielectric layer
14
has been formed on the bottom etch stop layer
12
. A cap layer
16
, formed from silicon oxide, for example, covers the low k dielectric layer
14
. The via hole
20
was previously formed in the low k dielectric layer
14
. Upon deposition and patterning of the photoresist material
18
, the mushroom shape
22
is observed due to the via poisoning. It is thought that the photoresist deposition and patterning process produces outgassing from the low k dielectric layer
14
to produce mushroom feature
22
and resist scum
24
within the trench pattern opening
26
.
The outgassing prevents the resist from properly getting into the via hole
20
so that it piles up on top of the via hole
20
. This outgassing problem leads to improperly formed topology on the wafer. The resist around the via hole
20
becomes very thick and difficult to pattern. When attempts are made to pattern and expose it, that area can not be exposed properly.
Attempts have been made to mitigate the via poisoning and resist scumming problem. One of these is to provide a baking step before the formation of the trench mask layer. Although this has been seen to help the via poisoning problem, it does not substantially eliminate the problem. Other methodology that has been attempted is to provide spin-on organic BARC in the via, but the relatively low adhesion of this material to the via sidewalls and bottom has caused this approach to fail in substantially eliminating via poisoning concerns. Another method to eliminate via poisoning concerns is to provide a thick layer of oxide within the via, but this has the disadvantage of undesirably reducing the via size.
There is thus a need for a method for substantially eliminating via poisoning concerns when forming a metal interconnect structure when low k dielectric material is employed in the interconnect structure.
SUMMARY OF THE INVENTION
These and other needs are met by the present invention which provides a method of forming an interconnect structure comprising the steps of forming a via hole in a low k dielectric, the via hole having a bottom and sidewalls. A bottom anti-reflective coating (BARC) is deposited by chemical vapor deposition (CVD) to cover the bottom and sidewalls of the via hole. A photoresist mask is then deposited and patterned on the low k dielectric layer. The patterned photoresist mask contains an opening that is at least partially over the via hole and low k dielectric layer.
By the provision of a CVD BARC that covers the bottom and sidewalls of a via hole, outgassing from the via hole is prevented during the formation of the photoresist mask on the low k dielectric layer. This has the result of substantially eliminating the via poisoning and resist scumming problem. The CVD BARC exhibits greater adhesion than the spin-on BARC of the prior art and therefore prevents outgassing more effectively than the spin-on BARC. Since the CVD BARC may be removed at the same time as the photoresist material of the photoresist mask, the via size is not reduced as in the prior art solutions that employed a thick oxide material in the via to prevent outgassing. Also, the process of depositing the BARC by the CVD process provides a high temperature that aids in the prevention of outgassing of the low k material in the via hole.


REFERENCES:
patent: 5946580 (1999-08-01), Wu
patent: 6096637 (2000-08-01), Sriram et al.
patent: 6114243 (2000-09-01), Gupta et al.
patent: 6156485 (2000-12-01), Tang et al.
patent: 6174800 (2001-01-01), Jang

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