Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-07-27
2004-03-30
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S476000, C438S594000, C438S623000, C438S758000, C438S769000, C438S770000, C438S778000, C438S787000, C438S789000, C438S790000
Reexamination Certificate
active
06713364
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating an insulator having a low dielectric constant in which the insulator is located between interconnects on a semiconductor substrate.
Electronic circuits that are connected to one another with electrical wiring are usually configured in semiconductor substrates. To that end, the electrical wiring is insulated from the semiconductor substrate by an insulating layer and the electronic components in the semiconductor substrate are connected to the metal wiring by so-called vias (contact holes). Since the electrical wiring has a row of interconnects which are formed relatively close together on the insulating layer, there is capacitive coupling between adjacent interconnects. The capacitive coupling between adjacent interconnects becomes greater, as the dielectric constant of the material located between the interconnects becomes higher. In this case, a large coupling capacitance has the disadvantage that electrical signals on the interconnects are delayed and attenuated by the high capacitance.
Undoped or doped silicon oxide, silicon nitride or silicon oxynitride layers are usually used as dielectric layers between interconnects on a semiconductor chip. These layers have dielectric constants of between 4 and 7. The increasing miniaturization of the structures has the effect that the distance between two interconnects keeps on decreasing. As a result, the coupling capacitance between adjacent interconnects keeps on increasing. In this case, the extent of capacitive coupling is directly proportional to the dielectric constant of the insulating material configured between two interconnects. Known insulators having a dielectric constant of less than 4 are e.g. fluorine-doped oxides and organic materials. However, these materials have integration problems during interaction with customary semiconductor fabrication processes such as RIE (reactive ion etching), CMP (chemical mechanical polishing) and thermal processes, since organic materials are, for example, too unstable for these fabrication methods.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating an insulator, between interconnects on a semiconductor substrate, which overcomes the above-mentioned disadvantageous of the prior art methods of this general type. In particular, it is an object of the invention to provide such a method to fabricate the insulator with a relatively low dielectric constant.
With the foregoing and other objects in view there is provided, in accordance with the invention a method for fabricating an insulator on a semiconductor substrate. The method includes steps of: providing a semiconductor substrate having a first interconnect and a second interconnect; forming amorphous silicon between the first interconnect and the second interconnect; anodically etching the amorphous silicon in a hydrofluoric-acid-containing electrolyte to convert the amorphous silicon into a porous silicon; and oxidizing the porous silicon to convert the porous silicon into a porous silicon oxide.
The advantage of the method is that well-known materials exhibiting good compatibility, such as silicon and silicon oxide, are used during the fabrication of the dielectric. A silicon oxide usually has a dielectric constant of 4, which can be reduced to values of between 1.1 and 4 through the formation of a porous silicon oxide. In this case, silicon oxide and porous silicon oxide are compatible with process steps such as RIE, CMP and thermal processes. Therefore, porous silicon oxide is outstandingly suitable for forming an intermetal dielectric.
By way of example, the formation of porous silicon is shown in “Spatial and quantum confinement in crystalline and amorphous porous silicon”, I. Solomon et al., Journal of Non-Crystalline Solids 227-230 (1998) 248-253, U.S. Pat. No. 5,935,410, and “Study of Photoluminescence in Porous Silicon Prepared by Electrochemical Etching of Amorphous silicon”, E. Bhattacharya et al., Physics of Semiconductor Devices, 603-606 (1998).
In accordance with an added feature of the invention, the conductive silicon is an amorphous silicon, a microcrystalline silicon, or a polysilicon. The aforementioned silicon structures are suitable for being converted into a porous silicon using a hydrofluoric-acid-containing electrolyte in an anodic etching process. In this case, porous silicon, involving a nanostructured material, is produced within a specific process regime. In this case, the degree of porosity can be varied between 20 and 90% by way of the process parameters. In this case, the porous silicon has a distinctly lower conductivity than the compact silicon from which it is formed.
In accordance with an additional feature of the invention, the conductive silicon is deposited on the substrate by an LPCVD (low pressure chemical vapor deposition) method, a PECVD (plasma enchanced chemical vapor deposition) method, or an RTCVD (rapid thermal chemical vapor deposition) method. The advantage of the aforementioned deposition methods is that the conductive silicon is deposited conformally on interconnects configured on the substrate surface. Furthermore, the aforementioned methods are suitable for filling interspaces between interconnects in a manner free from shrink holes. This has the advantage that fewer gas inclusions are formed in the dielectric layer.
In accordance with a concomitant feature of the invention, the oxidation of the porous silicon is carried out using an RTP (rapid thermal process) step, a furnace step, a plasma treatment or an anodic oxidation with the aid of oxygen. The aforementioned oxidation methods are advantageously suitable for forming a porous silicon oxide from the porous silicon.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for forming an insulator having a low dielectric constant on a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Bhattacharya et al.: “Study of Photoluminiscence in Porous Silicon Prepared by Electrochemical Etching of Amorphous Silicon” Physics of Semiconductor devices, 1998, pp. 603-606.
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Greenberg Laurence A.
Lebentritt Michael S.
Luhrs Michael K.
Mayback Gregory L.
Stemer Werner H.
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