Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-11-05
2001-02-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S790000, C438S787000
Reexamination Certificate
active
06187692
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87115243, filed Sep. 14, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for forming a thin insulating layer, which includes non-doped silicate glass (NSG) and is formed by two different temperatures.
2. Description of Related Art
In a semiconductor fabrication process with high integration, a stack structure is commonly used to increase device integration. The stack structure typically includes a device part, such as a metal-oxide semiconductor (MOS) transistor on a substrate and multiple over the substrate. Several insulating structures are needed for a purpose of isolation. For example, a field oxide (FOX) layer formed by a local oxidation (LOCOS) process on the substrate or a shallow trench isolation (STI) structure formed in the substrate is used to isolate the MOS transistor. Above the MOS transistor and the FOX layer, an insulating layer is necessary to be formed over the substrate to isolate the MOS transistor from the first layer of the interconnect metal layers. The insulating layer usually is made of tetra-ethyl-ortho-silicate (TEOS) silicon oxide because it has better step coverage and planarization capability.
FIG.
1
A and
FIG. 1B
are cross-section views of a portion on a substrate, schematically illustrating a conventional fabrication process for forming an insulating layer over the substrate that includes a FOX structure. In
FIG. 1A
, a FOX layer
116
is formed on a surface of a semiconductor substrate
100
to isolate a MOS transistor
105
, which includes a gate structure
115
, two interchangeable source/drain regions
112
,
114
. The gate structure
115
includes a gate
110
on the substrate
100
and a spacer
111
on each side of the gate
110
. The interchangeable source/drain regions
112
,
114
have a lightly doped drain (LDD) structure. In
FIG. 1B
, a metallization process is performed by first forming an insulating layer
118
over the substrate
100
in order to isolate the MOS transistor
105
from a metal layer (not shown) formed subsequently over the insulating layer
218
. The insulating layer
118
includes non-doped silicate glass (NSG), such as silicon oxide formed by using TEOS gas as a reaction gas in a chemical vapor deposition (CVD) process. The operation temperature is about between 400° C. and 500° C., and the operation pressure is about between 1 and 10 torrs.
FIG.
2
A and
FIG. 2B
are cross-section views of a portion on a substrate, schematically illustrating a conventional fabrication process for forming an insulating layer the substrate that includes a STI structure. In
FIG. 2A
, a shallow trench isolation (STI) structure
216
is formed in a semiconductor substrate
200
to isolate a MOS transistor
205
, which includes a gate structure
215
, two interchangeable source/drain regions
212
,
214
. The gate structure
215
includes a gate
210
on the substrate
200
and a spacer
211
on each side of the gate
210
. The interchangeable source/drain regions
212
,
214
have a lightly doped drain (LDD) structure. In
FIG. 2B
, a metallization process is performed by first forming an insulating layer
218
over the substrate
200
in order to isolate the MOS transistor
205
from a metal layer (not shown) formed subsequently over the insulating layer
218
. The insulating layer
218
includes NSG, such as silicon oxide formed by using TEOS gas as a reaction gas in a chemical vapor deposition (CVD) process. The operation temperature is about between 400° C. and 500° C., and the operation pressure is about between 1 and 10 torrs.
However, in FIG.
1
B and
FIG. 2B
, the substrates
100
,
200
include silicon and do not absorb water vapor. The FOX layer
116
and the STI structure
216
include oxide and have a strong property of absorbing water vapor. When the insulating layers
118
,
218
are formed over the substrates
100
,
200
by the conventional method, the deposition rate on the substrates
100
,
200
is larger than that on the FOX layer
116
and the STI structure
216
. This causes a non-uniform thickness of the insulating layers
118
,
218
. A surface sensitivity defined as a quantity of T
1
/T
2
is used to estimate the step coverage capability of the insulating layers
118
,
218
. T
1
is a thickness of the insulating layers
118
,
218
at a portion above the FOX layer
116
or the STI structure
216
, and T
2
is a thickness of the insulating layers
118
,
218
at a portion above the substrates
100
,
200
. By a conventional fabrication method, T
1
is usually about 2500 Å-3200 Å, and T
2
is usually about 4000 Å-5000 Å so that the surface sensitivity is about 62%, which implies a non uniform thickness. A severe non-uniform thickness does certainly affect subsequent fabrication processes. Moreover, a large number of voids
130
can occur on the insulating layers
118
,
218
at a portion above the FOX layer
116
and the STI structure
216
. The voids
130
can easily absorb water vapor and cause a failure of insulating function.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for forming an insulating layer, which can solve a problem of non-uniform thickness of the insulating layer, which includes NSG, such as a TEOS silicon oxide.
In accordance with the foregoing and other objectives of the present invention, a method for forming an insulating layer to solve a problem of non-uniform thickness of the insulating layer is provided. The method includes forming a first insulating layer over a substrate preferably by chemical vapor deposition (CVD) at a first operation temperature, which is lower than a conventional temperature. The thickness of the first insulating layer is thinner than a conventional thickness. The substrate includes, for example, a MOS transistor and an isolation structure to isolate the MOS transistor. A second insulating layer is formed over the first insulating layer preferably by CVD at a second temperature, which is higher than the first operation temperature. The thickness of the second insulating layer is larger and is sufficient large to achieve an insulating purpose.
REFERENCES:
patent: 5716891 (1998-02-01), Kodama
patent: 5804509 (1998-09-01), Cho
patent: 5908308 (1999-06-01), Barsan et al.
patent: 5943599 (1999-08-01), Yao et al.
Lan Shih-Ming
Lin Andrew
Liu Chun-Liang
Meng Hsien-Liang
Huang Jiawei
J. C. Patents
Jones Josetta
Niebling John F.
United Silicon Incorporated
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