Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2001-08-16
2004-09-07
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S197000, C438S152000, C438S723000
Reexamination Certificate
active
06787408
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming an electrical insulating layer during the semiconductor processes, and more particularly, to a method for forming an electrical insulating layer on bit lines of the flash memory.
BACKGROUND OF THE INVENTION
Since the main purpose of the flash memory's cell is to retain electrons for recording the desired information, it is considerably important to be able to maintain a long span of charge retention. Generally, the electrons will be lost due to the failure of the electrical insulating layer over the flash memory's cell. Especially, it is the key point of charge retention whether the electrical insulating layer has a good insulating characteristic with respect to silicon-oxide layer on the bit lines. The conventional method for fabricating an electrical insulating layer on the flash memory's cell is shown in
FIGS. 1-3
.
Referring to
FIG. 1
, a polysilicon layer
102
, a silicon nitride layer
104
and a cap layer
106
are sequentially formed on a gate region of a semiconductor substrate
100
. Thereafter, a lithography and etching process is used to form spacing
110
between gate stacks
108
. The silicon-oxide is filled into the spacing
110
by using a chemical vapor deposition (CVD) process. Since the structure of the silicon-oxide layer
112
formed by CVD process is undulated with the spacing
110
, the top surface of the silicon-oxide layer
112
between the spacing
110
has a recess
114
a.
Referring to
FIG. 2
, an etch back or chemical mechanical polishing (CMP) process is carried out to remove the silicon-oxide layer's
112
recess
114
a
. The silicon nitride layer
104
serves as a stop layer so that the silicon-oxide is left inside spacing
110
to form a spacing silicon-oxide layer
116
. According to the foregoing, since the top surface of silicon-oxide layer
112
is undulated with spacing
110
, the so-called conformity, the surface of the spacing silicon-oxide layer
116
must still keep a recessed profile after an etch back. If the CMP process is used to remove the redundant silicon-oxide, the spacing silicon-oxide layer
116
also forms a recess
114
b
due to dish effect. Finally, referring
FIG. 3
, while a silicon nitride layer
104
is removed, the recess
114
b
is generated on the surface of the spacing silicon-oxide layer
116
.
However, the recess
114
b
on the surface of the spacing silicon-oxide layer
116
has many disadvantages. The effective thickness
118
of the spacing silicon-oxide layer
114
is not enough to block a great deal of the impact of electrons but to severely destroy the bit lines (not shown in the figure) located under the spacing silicon-oxide layer
116
. Additionally, the tip
120
portion of the spacing silicon-oxide layer
116
will cause the film to crack when a deposition process is performed continuously. Further, after the silicon nitride layer
104
is removed, the step height between the polysilicon layer
102
and the spacing silicon-oxide layer
116
is too high so that the over-etching must be greatly increased but etching tolerance is inadequate resulting in the thin film's damage.
SUMMARY OF THE INVENTION
In view of the problems encountered with the foregoing conventional electrical insulating layer including the spacing silicon-oxide layer in the flash memory, the effective thickness of the spacing silicon-oxide layer is not sufficient and its profile is inferior to the one of the present invention.
As a result, the primary object of the present invention is to form a dielectric layer and a planarized layer, and adjusts the etching rate ratio between the dielectric layer and the planarized layer for generating the spacing dielectric layer, such as silicon-oxide, having a round top and slant sides to benefit the following processes.
Another object of the present invention is to increase the effective thickness of the spacing of the silicon-oxide layer for blocking the bit lines from an ion implantation process.
According to the above objects, the present invention sets forth a method for forming an electrical insulating layer on bit lines of the flash memory. First, a plurality of gate stacks are sequentially formed on the gate region of a semiconductor substrate wherein each of the gate stacks has a conductive layer, a mask layer and a cap layer, and the gate stacks are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate to cover the gate stacks and then to fill the spacing, and the dielectric layer is higher than the cap layer. A planarized layer is then formed on the dielectric layer to create a planar surface.
One etching step is utilized to entirely remove the dielectric layer located on the cap layer and thus spacing dielectric layer is formed inside the spacing. Afterwards, another etching step is used to remove the cap layer wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides to prevent a thin film of the following process from stress concentration. Finally, the mask layer is stripped and then the spacing silicon-oxide layer remains to form the electrical insulating layer on bit lines of the flash memory.
REFERENCES:
patent: 5637896 (1997-06-01), Huang
patent: 5814564 (1998-09-01), Yao et al.
patent: 5968610 (1999-10-01), Liu et al.
patent: 6080639 (2000-06-01), Huang et al.
patent: 6492214 (2002-12-01), Chen et al.
Chen Chien-Wei
Lai Jiun-Ren
Deo Duy-Vu
Dickinson Wright PLLC
Macronix International Co. Ltd.
Norton Nadine G.
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