Method for forming an arsenic doped dielectric layer

Details Method for forming an arsenic doped dielectric layer Method for forming an arsenic doped dielectric layer

2000-03-03

2001-11-27

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Utilizing reflow

C438S783000, C438S784000, C438S788000

Reexamination Certificate

active

06323137

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor manufacturing processes, and more particularly, to a method for forming an arsenic doped dielectric layer.
BACKGROUND OF THE INVENTION
Interlayer and intermetal dielectric layers are commonly used to isolate conducting structures, such as metal layers, from subsequently deposited conducting layers. These dielectric layers are also useful in performing a planarization function. Typical prior art processes for forming an interlayer dielectric layer consist of depositing multiple layers of oxide over the underlying metal layer.
One common type of oxide used in the formation process is tetraethylorthosilicate (TEOS, Si(OC
2
H
5
)
4
). The TEOS oxide can be deposited in conjunction with a dopant such as arsenic (As) in the form of triethylarsenite (TEAS, As(OC
2
H
5
)
3
) to form a doped oxide layer. The doped oxide layer is used as a source for n-type dopants. The process typically is a low pressure chemical vapor deposition (LPCVD) reaction in a batch type furnace. The reaction temperature is around 620° C. at a pressure of about 600 mTorr.
Because the prior art process is done in a batch furnace, thickness and dopant uniformity of the oxide may unacceptably vary from wafer to wafer. Additionally, the process temperature will increase the thermal budget loading for advanced integrated circuits. The process temperature may also result in dopant diffusion to regions outside of the deposited oxide. The elevated process temperature will also cause a higher rate of thermal dissociation of the TEAS relative to the TEOS, resulting in difficulty in controlling doping concentration within the batch. As a related problem, because arsenic is the dopant, the high toxicity of arsenic results in difficulty in safely maintaining and troubleshooting the manufacturing process.
Thus, what is needed is a method of forming doped oxide with greater uniformity of thickness and at a lower temperature.
SUMMARY OF THE INVENTION
A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting said process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr, flowing tetraethylorthosilicate (TEOS) into said process chamber; flowing triethylarsenate (TEAS) into said process chamber; and flowing ozone into said process chamber.


REFERENCES:
patent: 6218319 (2001-04-01), Dutron et al.

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