Method for forming aligned vias under trenches in a dual...

Details Method for forming aligned vias under trenches in a dual... Method for forming aligned vias under trenches in a dual...

1998-06-19

2001-04-24

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S633000, C438S638000

Reexamination Certificate

active

06221759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of semiconductor devices, and more particularly to a method for encapsulating a metal via in a damascene process.
2. Description of the Related Art
Since the introduction of semiconductor devices, the size of semiconductor devices have been continuously shrinking, resulting in smaller semiconductor chip size and increased device density on the chip. One of the limiting factors in the continuing evolution toward the smaller device size and higher density has been the interconnect area needed to route interconnect lines between devices. As a way to overcome such a limitation, multilevel interconnection systems have been implemented using shared interconnect lines between two or more levels.
Originally, conventional process techniques implemented multilevel interconnection systems by depositing a metal layer, photomasking the deposited metal layer, and then etching the metal layer to form a desired interconnection. However, since metals are typically more difficult to pattern and etch than other semiconductor layers such as dielectric or oxide layers, dual damascene process has been implemented to form metal vias and interconnects by dispensing entirely with the metal etching process. Dual damascene process is a well known semiconductor fabrication method for forming metal vias and interconnect lines.
In conventional dual damascene processes, a via and a trench are etched in an oxide layer such as an intermetal dielectric layer. The dielectric layer is typically formed over a metal layer. The via and the trench are then filled with a metal (e.g., Al, Cu) in the vias and trenches to form the metallization vias and interconnect lines, respectively. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) process.
Dual damascene process is gaining wider application in semiconductor process because it offers significant advantages over conventional process of etching metals. For example, it does not require etching of metals, such as copper and to a lesser degree, aluminum, which are more difficult to pattern and etch than dielectric materials. Additionally, the dual damascene process involves less process steps than conventional techniques that form vias as a separate step.
In general, however, a via or a trench becomes progressively more difficult to fill completely when the depth of the via or trench increases with respect to the width. In this context, the ratio of the depth to the width of a via or trench is referred to as “aspect ratio.” The higher aspect ratio of the via and trench, the more difficult it becomes to fill them completely. Since a via is typically formed directly beneath a trench in a conventional dual damascene process, the height (i.e., depth) of the via and trench combination is generally is greater than either a via or a trench alone. The greater depth of the via and trench combination thus leads to voiding problem when metal is filled in the via and trench during the dual damascene process.
The voiding problem is particularly problematic for the via because the via is generally smaller in width (e.g., diameter) than the trench but has a greater depth from the opening of the trench to the bottom of the via. Furthermore, during the dual damascene process, the via is often formed in a mis-aligned fashion with respect to the trench above. The improper alignment between the via and the trench may significantly increase the aspect ratio of the via. For example, when the trench is not formed directly above the via, the width or the opening of the via decreases, which typically leads to voiding in the via when filled with a metal. Additionally, when a mis-aligned via is formed at the end of a metal interconnect line, the aspect ratio further increases due to line shortening effects during lithography.
The problem of a mis-aligned via with high aspect ratio, which leads to a voiding effect is illustrated in Prior Art
FIGS. 1A and 1B
. Prior Art
FIG. 1A
shows a cross sectional view of a silicon wafer stack
100
formed by a conventional dual damascene process. The wafer stack
100
includes a semiconductor substrate
102
, an oxide layer
104
, a metal layer
106
, a first intermetal oxide (IMO) layer
108
, a second IMO layer
110
, and a third IMO layer
112
. The metal layer
106
is formed over the oxide layer
104
, which is formed over the substrate
102
.
The wafer stack
100
has a via
114
, which is mis-aligned with respect to a trench
116
formed over the via
114
. That is, the position of the via
114
is skewed to one side and is not disposed in the center of the metal layer
106
or the trench
116
. The depth of the via
114
is significantly greater than the width or the opening of the via
114
. Accordingly, the aspect ratio of the via is relatively high.
Prior Art
FIG. 1B
illustrates the wafer stack
100
after filling the via
114
and the trench
116
with a metal
122
and a barrier layer
118
. Due to the high aspect ratio of the via
114
, metal
122
does not fill the via
114
completely. That is, a void is formed within the via
114
.
As illustrated in Prior Art
FIG. 1B
, a result of the mis-aligned via with a high aspect ratio is the formation of void within the via when the via is subsequently filled with a metal. The void often forms due to the high aspect ratio of the via. Subsequently, the void within the filled via may cause reliability problem in an integrated circuit and lead to failure of a semiconductor device. In addition, the mis-aligned via typically results in a smaller overlap area between the via and the trench. The smaller overlap area generally increases via resistivity during operation. The mis-aligned vias with consequent high aspect ratios result in reduced process margins, lower yield, and lower reliability of semiconductor devices.
In view of the foregoing, what is needed is a method for forming a properly aligned via with a trench in a dual damascene process. In addition, what is also needed is a method for preventing voids in a metal via to ensure fabrication of more reliable semiconductor devices.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a method for a method for forming aligned vias under trenches in a dual damascene process. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and the first metal layer is formed over a semiconductor substrate. The method includes forming an etch stop layer over the oxide layer and forming a set of adjacent trenches in the oxide layer through a portion of the etch stop layer. The method also includes forming a resist layer at least partially over the etch stop layer. The resist layer is formed in a via pattern to expose the set of adjacent trenches through the via pattern. The method further includes etching the oxide layer under the set of adjacent trenches until the oxide layer is etched through to expose at least a portion of the first metal layer so as to form a via under each of the adjacent trenches. In this process, the etch stop layer inhibits the oxide layer underneath from being etched substantially such that each of the vias formed under the each of the adjacent trenches is substantially of a same width as and in alignment with the associated trench above.
In another embodiment, the present invention provides a method for forming a via aligned with a trench to prevent voiding in a dual damascene process. The trench is formed in an intermetal oxide (IMO) layer that is formed over a first metal layer. A first metal layer formed over a semiconductor substra

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