Method for forming a void free via

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S750000, C257S734000, C257S741000

Reexamination Certificate

active

06977437

ABSTRACT:
A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

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patent: 2002/0096768 (2002-07-01), Joshi

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