Method for forming a via in a damascene process

Details Method for forming a via in a damascene process Method for forming a via in a damascene process

2002-04-10

2004-10-12

Zarnela, David A. (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S713000

Reexamination Certificate

active

06803305

ABSTRACT:

FIELD OF THE INVENTION
The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a method for forming a via in a damascene process.
BACKGROUND ART
As semiconductor geometries continue to become smaller and smaller, new difficulties arise in the fabrication of the correspondingly smaller features. As one example, when device sizes decrease in size (in order to form more devices on each wafer), features such as vias have critical dimensions (CDs) which become considerably smaller. The reduced CD of, for example, a via has certain drawbacks associated therewith. Referring now to Prior Art
FIG. 1A
, a side sectional view of a via formed in a damascene process wherein the via has a reduced CD is shown. In Prior Art
FIG. 1A
, a substrate
100
has a via
102
formed therein using a damascene process. In the structure of Prior Art
FIG. 1A
, the critical dimension (CD) is shown as the width, W, at the top of via
102
. Furthermore, via
102
has a depth, D.
Referring still to Prior Art
FIG. 1A
, as the CD of via
102
decreases, significant manufacturing difficulties arise. For example, in a damascene process, such a via is typically formed using a plurality (e.g. two major etches for the formation of via
102
) of anisotropic etches in order to etch a sufficient depth into substrate
100
while still maintaining the desired CD for via
102
. As a result, sharp corners, typically shown as
104
a
and
104
b
and
106
a
and
106
b
, are formed at the top edges present within via
102
. Sharp corners
104
a
and
104
b
induce stress in subsequently deposited overlying layers and reduce adherence of the overlying layer to underlying substrate
100
.
With reference now to Prior Art
FIG. 1B
, a side sectional view of via
102
of Prior Art
FIG. 1A
is shown having an overlying layer of material disposed thereon. As shown in Prior Art
FIG. 1B
, due to the presence of sharp corners (e.g. corners
104
a
,
104
b
,
106
a
, and
106
b
) and the profile of via
102
, voids (typically shown as
108
) are formed in the overlying layer of material. These voids deleteriously affect the integrity of the device, and may ultimately lead to failure of the device in which the void-containing via is used.
As critical dimensions of vias formed using the damascene process continue to decrease in size, it is expected that the above-described problems will be further exacerbated. Additionally, any attempts to eliminate or reduce the problems associated with damascene process-formed vias should be compatible with existing semiconductor fabrication processes such that a complete retooling of conventional semiconductor fabrication facilities is not required.
Thus, a need exists for a method for forming a via in a damascene process wherein the via does not suffer from poor adherence to a subsequently deposited overlying layer. Still another need exists for a method for forming a via in a damascene process which enables the formation of a metallized interconnect wherein the method meets the above need and wherein the metallized interconnect does not suffer from void/seam formation. Yet another need exists for a method for forming a via in a damascene process wherein the method meets all of the above-listed needs and wherein the method is compatible with existing semiconductor fabrication processes.
SUMMARY OF INVENTION
The present invention provides a method for forming a via in a damascene process wherein the via does not suffer from poor adherence to a subsequently deposited overlying layer. The present invention further provides a method for forming a via in a damascene process which enables the formation of a metallized interconnect wherein the method achieves the above accomplishment and wherein the metallized interconnect does not suffer from void/seam formation. The present invention also provides a method for forming a via in a damascene process wherein the method achieves all of the above-listed accomplishments and wherein the method is compatible with existing semiconductor fabrication processes.
In one embodiment of the present invention, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.
In another embodiment, the present invention includes the steps of the above-described embodiment, and further includes the step of depositing a layer of a conductive material into the via having the profile conducive to the adherence of overlying material thereto. After the deposition of the conductive material, the present embodiment performs a planarization step such that the conductive material remains primarily within the via. As a result, the present embodiment provides a metallized interconnect within a via formed in a damascene process, wherein the metallized interconnect is substantially free of voids.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.


REFERENCES:
patent: 6424038 (2002-07-01), Bao et al.
patent: 6440838 (2002-08-01), Lui et al.
patent: 6566260 (2003-05-01), Chooi et al.

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