Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-08
2001-08-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S694000, C438S695000, C438S703000, C438S706000, C438S709000, C438S711000
Reexamination Certificate
active
06274493
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87119383, filed November 23, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a via. More particularly, the present invention relates to a method for removing a photoresist layer.
2. Description of Related Art
In order to increase integration of semiconductor devices, multilevel metallization processes are widely used in metal oxide semiconductors (MOS). In a multilevel metallization process, an inter-metal dielectric (IMD) layer is necessarily formed between every two layers of metal for insulation. A via is formed in the inter-metal dielectric layer to electrically couple the metal lines.
However, stacks of a conductive layer/an insulating layer/a conductive layer cause what is known as a parasitic capacitor effect, in which a parasitic capacitor is formed. Thus, RC delay time generated by the parasitic capacitor effect causes a decrease in device operating speed. Therefore in order to lower the parasitic capacitor effect, an insulating layer with a low dielectric constant is provided between every two metal lines. Flowable oxide is commonly used as the insulating material.
One method of forming the inter-metal dielectric layer is to form a conformal barrier oxide layer, a flowable oxide layer and a cap oxide layer over a semiconductor substrate. Additionally, an insulating layer can be formed between the flowable oxide layer and the cap oxide layer. The inter-metal dielectric layer has a low dielectric constant so as to decrease the parasitic capacitor effect.
In a conventional method of forming a via, using a patterned photoresist layer as an etching mask, the inter-metal dielectric layer is etched until the metal line is exposed to form a via hole in the inter-metal dielectric layer. The photoresist layer is removed by oxygen plasma. The substrate is washed with a solvent to remove the photoresist layer remaining on the substrate. While forming the via, the flowable oxide layer is exposed by the via. Therefore during the step of removing the photoresist layer with oxygen plasma, the flowable oxide layer is bombarded by the oxygen plasma. After the substrate is washed with a solvent, the number of Si—H bonding in the flowable oxide layer is decreased and the number of Si—OH bonding is increased.
The increased number of Si—OH bonding leads to an increase in the dielectric constant of the flowable oxide layer so that parasitic capacitor's capacitance is increased. Then, RC delay time is increased, which causes a decrease of device operating speed. In addition, an increased Si—OH bonding causes moisture contained by the flowable oxide to increase. In a later process of filling the via hole with a conductive layer, bubbles are formed from the moisture that exists in the flowable oxide due to the high temperature process; in other words, the bubbles are generated in the via. The bubbles poison the conductive material that fills the via hole, resulting in a poisoned via phenomenon. Thus, the conductive line cannot be electrically coupled, and devices malfunction. Device yield is decreased.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of forming a via, which can avoid an increase in the dielectric constant of an inter-metal dielectric layer generated by the change of the flowable oxide's bonding. It can also avoid generating bubbles in the via. Therefore, a poison phenomenon, which could cause a decrease of the device yield, does not occur.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a via on a semiconductor substrate wherein a conductive line is formed thereon and an inter-metal dielectric layer is formed over the conductive line. A patterned photoresist layer is formed on the inter-metal dielectric layer. A portion of the inter-metal dielectric layer is removed to expose the conductive line using the photoresist layer as a mask to form a via hole, wherein the via hole is subsequently used to form a via. A high density plasma process is performed to remove the photoresist layer. A cleaning step with a solvent is performed to remove the photoresist layer remaining on the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5818111 (1998-10-01), Jeng et al.
patent: 5948701 (1999-09-01), Chooi et al.
patent: 6028367 (1999-05-01), Yu
Berry Renee R
Huang Jiawei
J. C. Patents
Nelms David
United Microelectronics Corp.
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