Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-07-27
2004-01-06
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S404000, C438S408000, C438S239000, C438S243000, C438S248000
Reexamination Certificate
active
06673693
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for producing a trench in a semiconductor substrate.
Semiconductor substrates are used to form electronic circuits and memories. By way of example, DRAMs (Dynamic Random Access Memory) are used as memories. These are dynamic random access memories. A DRAM chip contains an array of memory cells which are configured in the form of rows and columns and are driven by word lines and bit lines. A DRAM memory cell usually contains a transistor connected to a capacitor. Two basic concepts are customary for the capacitors, one concept provides a so-called stacked capacitor and the second concept provides a so-called trench capacitor. In order to form a trench capacitor with a large capacitance, it is necessary to form the trench capacitor with a large capacitor area. Since the substrate surface used by a memory cell decreases step-wise, one possibility for increasing the capacitance of the trench capacitor consists in forming a deeper trench (deep trench), in the substrate.
To date, trenches have been etched in a substrate such as silicon by performing reactive ion etching (RIE). First, a hard mask is formed on the substrate surface in order to cover the regions of the substrate surface which are not to be etched. The patterning of the hard mask is usually effected conventionally using a resist mask and subsequent lithography. As a result of the progressive miniaturization of circuits and the associated decrease in the trench diameters, the aspect ratio (ratio of trench depth to trench diameter) of a capacitor can increase while the capacitance remains the same. What is disadvantageous in this case is that reactive ion etching can only form trenches with limited aspect ratio.
As an example, V. Lehmann and H. Voll, “Formation mechanism and properties of electrochemically etched trenches in n-type silicon” J. Electrochemical Society 137 (1990) 653, describe a method in which trenches are formed by electrochemically etching a substrate in electrolytes containing hydrofluoric acid. Trenches having a larger aspect ratio are made possible by this method, but this method cannot be performed economically because of its low etching rate and its high current consumption.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for forming a trench in a semiconductor substrate which overcomes the above-mentioned disadvantageous of the prior art methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for forming a trench in a semiconductor substrate that includes the following steps: providing a substrate having a substrate surface; providing a mask having a window and configuring the mask on the substrate to define an uncovered portion of the substrate surface that is within the window; electrochemically etching the substrate, proceeding from the uncovered portion of the substrate surface that is within the window; forming a porous substrate in a trench-shaped region proceeding from the substrate surface; and completely removing the porous substrate from the trench-shaped region.
The present method for forming trenches involves electrochemically etching only 20% to 80% of the substrate that is configured in the trench. This is in contrast to the method described by Lehmann in which all of the substrate that is configured in the trench is etched. This is made possible by suitable variation of the process parameters. Since only a fraction of the substrate is electrochemically etched from the region of the trench, the throughput rate can be increased to a multiple and the current consumption can be reduced to a fraction. A porous substrate remains within the electrochemically etched trench region. Once the desired trench depth is reached, the electrochemical etching process can be ended. Afterward, the porous network of the substrate in the trench region can be removed very rapidly and without further lithographic exposure steps. The trench is advantageously formed with a shape corresponding to the porous trench-shaped substrate region previously formed.
The process sequence specified describes a novel fabrication process for trenches in microelectronics.
In accordance with an added feature of the invention, the porous substrate has a density of between 20% and 80% of the original substrate. The lower the amount of the substrate that is electrochemically etched by the etching, correspondingly, the lower is the amount of the current that is consumed. Consequently, the etching process is ended more quickly, which means economic advantages.
In accordance with an additional feature of the invention, the porous substrate in the trench is etched using an alkaline etchant. The advantage of the alkaline etchant is that it is suitable for removing a porous substrate from a trench.
In accordance with a further feature of the invention, KOH is used as the etchant. KOH is advantageously suitable for etching silicon.
In accordance with a further added feature of the invention, the porous substrate is oxidized and porous substrate oxide is formed. The porous substrate is advantageously oxidized into porous substrate oxide thereby enabling the use of further etchants that are suitable for removing substrate oxide.
In accordance with a further additional feature of the invention, the etchant contains hydrofluoric acid.
In accordance with a concomitant feature of the invention, the substrate contains silicon.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for forming a trench in a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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C.M.A.Ashruf et al.: “Galvanic porous silicon formation without external contacts” Sensors and Actuators 74 (1999), pp. 118-122.
V.Lehmann et al.: “Formation Mechanism and Properties of Electrochemically Etched Trenches in n-Type Silicon”, J.Electrochem. Soc., vol. 137, No. 2, Feb. 1990.
Infineon - Technologies AG
Mayback Gregory L.
Pham Long
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