Method for forming a transistor having gate dielectric...

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S300000, C438S305000, C438S528000, C257SE21431

Reexamination Certificate

active

07927989

ABSTRACT:
A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

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patent: 2007/0298558 (2007-12-01), Yamauchi et al.
patent: 2009/0068810 (2009-03-01), Tsai et al.
Hortsmann et al; “Integration and Optimization of Embedded-SiGe, Compressive and Tensile Stressed Liner Films, and Stress Memorization in Advanced SOI CMOS Technologies”; Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International Dec. 5-7, 2005 pp. 233-236.
Yamashita et al: “Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond”; Future of Electron Devices, 2004. International Meeting for Jul. 26-28, 2004 pp. 123-124.

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