Method for forming a transistor for reducing a channel length

Details Method for forming a transistor for reducing a channel length Method for forming a transistor for reducing a channel length

2005-12-30

2008-10-07

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S163000, C438S154000, C438S180000, C438S229000, C438S230000, C438S231000, C438S232000, C438S585000, C257SE21433

Reexamination Certificate

active

07432144

ABSTRACT:
A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.

REFERENCES:
patent: 5688703 (1997-11-01), Klingbeil et al.
patent: 7170139 (2007-01-01), Pan
patent: 7332387 (2008-02-01), Chu
patent: 2003-0013624 (2003-02-01), None

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