Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-01-31
2002-04-16
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S719000, C438S720000, C438S723000
Reexamination Certificate
active
06372652
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage, or for forming a thin-film laser blowable fuse with reproducible blowing power.
2) Description of the Prior Art
In modern semiconductor design, it is often desirable to provide polysilicon or other thin film fuses which can be selectively blown based upon the results of circuit testing. For example, several resistors can be designed in parallel, each having a fuse. One or more of the fuses can then be blown depending upon test results to trim the resistance of the group of parallel resistors and achieve the desired circuit characteristics.
To increase manufacturing productivity, circuit testing is frequently performed using an automatic tester. Productivity can be further increased by programming the automatic tester to electrically blow selected fuses during the automatic test cycle. However, to do this, the fuses must have a reproducible blowing wattage across the wafer and wafer to wafer.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,895,262 (Becker et al.) shows a fuse window etching method using a patch layer over a dielectric layer over a fuse, wherein the fuse comprises a conductive layer with an overlying silicon nitride layer. A stack of dielectric layers overlying the patch are etched by an etch process selective to the patch material; the patch material is etched using an etch which is not selective to the patch material; and the dielectric material overlying the fuse is etched using an etch method selective to silicon nitride. This invention teaches that the patch layer is preferably composed of polysilicon or silicon nitride.
U.S. Pat. No. 5,821,160 (Rodriguez et al.) teaches a polysilicon etch stop layer over a fuse dielectric layer.
U.S. Pat. No. 5,851,903 (Stamper) recites a tungsten barrier layer between fuses.
U.S. Pat. No. 5,879,966 (Lee et al.) teaches a protective coating over a fuse opening.
U.S. Pat. No. 5,760,453 (Chen) discloses a barrier layer over a fuse.
U.S. Pat. No. 5,729,041 (Yoo et al.) and U.S. Pat. No. 5,888,851 (Motonami et al.) show a protective film over a fuse window.
U.S. Pat. No. 5,891,762 (Sakai et al.) shows a polysilicon layer formed over a fuse concurrently with a cell plate and used as a fuse window etch stop.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage.
It is another object of the present invention to provide a method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage by controlling the thickness of a fuse dielectric layer overlying the fuse element using a sacrificial metal patch overlying the fuse dielectric layer and a two step etch wherein the first etch step etches a dielectric layer overlying the sacrificial metal patch selective to the material of the sacrificial metal patch and the second etch step etches the sacrificial metal patch selective to the fuse dielectric layer.
It is another object of the present invention to provide a method for forming a semiconductor device with a thin-film, electrically blowable fuse with a reproducible blowing wattage or a thin-film, laser blowable fuse with reproducible blowing power with a reduced number of processing steps.
It is another object of the present invention to provide a method for forming an blowable fuse and a ring surrounding the blowable fuse from the same layer of conductive fuse material to provide uniform topography and dielectric thickness both in dense areas and open areas of a circuit.
It is yet another object of the present invention to provide a method for forming an electrically blowable fuse with improved reliability by terminating the fuse window opening above the tapered portion of the fuse element so that the metal contacts are not affected by cracking and heating when the fuse element is blown.
To accomplish the above objectives, the present invention provides a method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.
The present invention provides considerable improvement over the prior art. The inventors have determined that the thickness of the fuse dielectric layer is critical for an electrically blowable fuse with a reproducible blowing wattage. Blowing wattage is a function of the resistance of the fuse element and the thickness of the use dielectric layer overlying the fuse element when it is blown. To electrically blow a fuse, the fuse element must be vaporized. If the fuse dielectric layer is too thick, vaporization is difficult and the fuse is poorly blown. However, if the fuse dielectric layer is too thin, then the fuse element will be attacked by the etch used to form a fuse window, and the resistance of the fuse element will be altered, changing the blowing wattage. The present invention provides good control over the thickness of the fuse dielectric layer, thereby providing a reproducible blowing wattage.
By forming the fuse element as part of the poly-1 layer, forming the fuse dielectric layer as part of the inter-layer dielectric layer, and/or forming the patch layer as part of the metal-1 layer, a device can be formed with an electrically blowable fuse with a reproducible blowing wattage using a reduced number of processing steps. Nitride or other dielectric film patches require additional (non-standard to CMOC or Bipolar or BiCMOS process) depositions and/or masking steps.
Also, by forming the fuse opening over the tapered portion of the fuse element the semiconductor device reliability is increased. The fuse element cracks and vaporizes in the narrow potion. By terminating the fuse opening over the tapered portion of the fuse element, the metal contacts are away from the cracking point, and the metal is not melted when the fuse is blown.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5578861 (1996-11-01), Kinoshita et al.
patent: 5729041 (1998-03-01), Yoo et al.
patent: 5747868 (1998-05-01), Reddy et al.
patent: 5748685 (1998-05-01), Reddy et al.
patent: 5760453 (1998-06-01), Chen
patent: 5821160 (1998-10-01),
Chu Shao-Fu Sanford
Sarkar Manju
Shafi Zia Alan
Shan Yu
Verma Purakh Raj
Chartered Semiconductor Manufacturing Ltd.
Deo Duy-vu
Pike Rosemary L. S.
Saile George O.
Utech Benjamin L.
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