Method for forming a silicide layer of semiconductor device

Details Method for forming a silicide layer of semiconductor device Method for forming a silicide layer of semiconductor device

2002-12-24

2003-12-23

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S682000, C438S721000, C438S755000

Reexamination Certificate

active

06667233

ABSTRACT:

BACKGROUND
1. Technical Field
A method for forming a silicide layer of a semiconductor device is disclosed, and, in particular, in the disclosed method, the silicide layer has a low specific resistance and chemical stability and is positioned below a portion where a defective layer is formed, thereby improving at least one operational property of the resultant CMOS.
2. Description of the Related Art
A silicide layer has a resistance 20 times lower than that of a source/drain region or a polysilicon gate. The silicide layer is essentially used in the CMOS. The silicide layer improves an operation speed which is one of the major factors which indicate an operational property of a semiconductor device.
The silicide layer is formed by depositing a thin metal film on a semiconductor substrate and thermally treating the resulting structure. Since the silicide layer has a low specific resistance and chemical stability and is positioned below portion where a defective layer is formed, it is used in the most of the contact processes.
As the semiconductor device is highly integrated, a parasitic resistance as well as a channel resistance existing below a gate increases in a degradation of the performance of the device. Therefore, the silicide layer having a lower resistance than a silicon is used in the source/drain region or polysilicon gate to manufacture the semiconductor device.
In the conventional art, the silicide layer is formed by performing a furnace annealing process wherein a metal such as Ti or Co reacts with Si, and more recently a rapid thermal annealing (RTA) process has been used due to prevalence of the RTA equipment.
In the conventional RTA process, a primary thermal annealing process is performed at a low temperature. As a result, Ti reacts with Si to form C
49
-TiSi
2
or TiSi, and Co reacts with Si to form CoSi.
An electric specific resistance of the two metals is very high, approximately 100 &mgr;&OHgr;·cm. Therefore, a secondary thermal annealing process is carried out to lower the specific resistance at a high temperature ranging from 800 to 900° C. with about 20° C. sec increase. Here, Ti forms crystalline C
54
-TiSi
2
and Co forms crystalline CoSi
2
.
the conventional RTA process, a deterioration phenomenon called agglomeration at the grain boundary of silicide grains and Si due to a high temperature and a low rise speed of a temperature. When Ti or Co having a unit thickness reacts with Si to respectively form TiSi
2
or CoSi
2
, Ti and Co consumes about 2.2 times and 3.6 times of the substrate, respectively.
Especially, CoSi
2
which is more than 50% thicker than TiSi
2
, reduces a physical distance between the CoSi
2
and Si diode junction interface in the source/drain region, which results in an excessive junction leakage current.
As described above, the conventional silicide layer decreases an actual width of the junction interface due to large consumption of the substrate. A shallow junction cannot be formed in a small device. In addition, excessive junction leakage current is generated thereby deteriorating the properties of the silicide layer.
SUMMARY OF THE DISCLOSURE
Accordingly, a method for forming a silicide layer of a semiconductor device is disclosed wherein a shallow junction can be formed in a very small device, and which minimizes the deterioration of an electrical property of the semiconductor device by reducing junction leakage current, when the silicide layer is formed using Ti and Co as source materials.
In order to achieve this improved performance, a method for forming a silicide layer of a semiconductor device is disclosed which comprises: (a) forming a lower insulating layer having a contact hole partially exposing an impurity junction region of a transistor on a semiconductor substrate; (b) forming a metal layer on the semiconductor substrate including the exposed portion of the impurity junction region and the sidewall of the contact hole; (c) performing a thermal annealing process by raising the temperature of the semiconductor substrate up to 600° C. at a speed ranging from 20 to 50° C. second; (d) performing a thermal annealing process by raising the temperature of the semiconductor substrate up to a range from 800 to 900° C. at a speed ranging from 200 to 300° C. second, wherein the semiconductor substrate is maintained at the highest temperature for less than one second; (e) forming a silicide layer on the impurity junction dropping temperature of the semiconductor substrate to below 700° C. at a speed ranging from 70 to 90° C. second; and (f) removing the non-reacted metal layer from the semiconductor substrate.
In addition, the impurity junction region is formed by using a 1×e
15
to 3×e
15
ions/cm
2
dose of As
75
with an ion implantation energy ranging from 15 to 30 KeV in case of an n-type transistor, and the impurity junction region is formed by using a 1×e
15
to 3×e
15
ions/cm
2
dose of BF
2
with an ion implantation energy ranging from 10 to 20 KeV in case of a p-type transistor. The metal layer is Ti layer or Co layer. Parts (c) and (d) can be consecutively performed in one equipment. Here, parts (c) and (d) are performed by rotating semiconductor substrate at the atmosphere of N
2
gas, at a state of O
2
free. Part (f) is performed using one of H
2
SO
4
solution and NH
4
OH solution.
A high rise speed of a temperature, a high drop speed of a temperature and a temperature are controlled through Spike RTA equipment so that an amorphous phase can be easily transformed to a crystalline phase. In addition, agglomeration with the implanted impurity is reduced due to deep reaction into the semiconductor substrate, and the time period during which the semiconductor substrate is maintained at a process temperature is controlled, thereby forming a complete crystalline silicide layer according to reaction between a metal Ti or Co and Si.
Moreover, a shallow junction can be formed and a junction leakage current property of the device can be improved by adjusting a physical distance between a silicide layer and Si diode junction interface in a source/drain region.


REFERENCES:
patent: 5648287 (1997-07-01), Tsai et al.
patent: 5998873 (1999-12-01), Blair et al.
patent: 6162675 (2000-12-01), Hwang et al.
patent: 6255701 (2001-07-01), Shimada
patent: 6271120 (2001-08-01), Huang et al.

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