Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-05-09
2004-11-09
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S773000, C257S774000, C257S776000, C438S128000, C438S597000, C438S618000, C438S620000, C438S635000
Reexamination Certificate
active
06815820
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductors, and more specifically, to the manufacture of interconnect structures within semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductors are designed pursuant to specific design rules that must be met in order to successfully manufacture an integrated circuit with a targeted process. Such design rules involve a variety of performance tradeoffs including speed versus power, resistance versus capacitance, electro-migration versus area, and others. These tradeoffs are the result of process limitations. For example, for a given conductor only one thickness of a specified metal layer may be used.
Various compensation methods are used to balance these tradeoffs. Standard techniques involve thin metals being used first in the construction of the circuit in order to minimize the impact of capacitance. The larger the cross sectional area a conductor has, the more capacitive coupling to neighboring metals the conductor has. Additionally, the use of dielectric materials adjacent a conductor creates an inherent capacitor. Advanced interconnect processes are characterized by having thin dielectric layers. Thin dielectrics result in conductors that have less capacitance but more resistance. Others have used various dielectric materials, such as low K (low dielectric constant) materials, to reduce capacitive coupling between conductors. Disadvantages of low K dielectrics include mechanical stability, defectivity, compatibility with metalization techniques and expense.
Metals having larger widths or vertically thicker dimensions are therefore used to minimize the impact of resistance. However, having a larger cross sectional area for a conductor results in a lower resistance, but also produces a larger circuit and typically higher capacitance.
A result of these characteristics is to use a hierarchical scheme within a multiple layer semiconductor where each layer is designed specifically to have differing conductor dimensions tailored to a specific capacitance/resistance tradeoff. Complex routing schemes are often required to connect these various layers in order to obtain an optimal balance of capacitance and resistance. These complex routing schemes result in larger integrated circuits and more expensive processes as a result of more processing steps being required. Present designs using existing known processes are limited in performance and size by balancing the tradeoffs inherent in capacitive/resistive tradeoffs.
A known compensation method is to use multiple layers of metal for a design. For example, multiple layers in the amount of nine to twelve are implemented and future processes will have the capability for many more. The multiple layers provide a designer with various resistance/capacitance properties so that a designer may select a particular metal layer for a predetermined function based upon the desired electrical characteristic. Several disadvantages that are inherent in the use of more metal layers include additional processing costs associated with such layers and additional size. Via layers are required to connect two or more conductors and such via layers tend to be defect prone for various reasons. Therefore, it is desired to minimize the need for and use of via layers.
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Farkas Janos
Lii Yeong-Jyh T.
Sanchez Hector
Strozewski Kirk J.
Yu Kathleen C.
Clingan, Jr James L.
Forde Remmon R.
King Robert L.
Tran Minhloan
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