Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-06-24
2001-07-17
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S132000, C438S467000
Reexamination Certificate
active
06261937
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to fuses and more particularly to fuses used in semiconductor integrated circuits.
As is known in the art, many modern semiconductor integrated circuits include fuses to protect sensitive parts during the manufacturing process as well as for the activation of redundant circuits, such as redundant memory cells in the case of Dynamic Random Access Memories (DRAMs). There are typically two types of fuses; a laser-blowable fuse, and an electrically (e.g. current) blowable-fuse. Electrically blowable fuses provide advantage over laser-blowable fuses in terms of size.
One technique used in the fabrication of an electrically blowable fuse is to cover the fuse material with surrounding dielectric material, such as silicon dioxide or BPSG material. After the fuse material has blown however, over time the material may migrate (i.e., heal) and provide an unwanted short circuit condition. Further, when the fuse is blown, mechanical forces in the surrounding dielectric are produced which may generate cracks in the dielectric material as it expands from the explosion of the fuse material. These explosion effects may damage other neighboring fuses.
In another technique, a cavity is formed over the fuse. Thus, when the fuse is blown to provide a open circuit, the fuse material becomes somewhat contained within the provided cavity. With DRAMs, these fuses are typically doped polycrystalline silicon having an upper layer of tungsten silicide. Further, these fuses are typically formed with the formation of the gate electrodes of the DRAM cells. While the gate electrodes are formed over active regions in the semiconductor, the fuses are typically formed over silicon dioxide isolation regions used to electrically isolate the active regions. The cavity is sometimes formed by a specific photolithographic step which opens an aperture in a mask over the fuse area while the remainder of the chip (i.e., the active regions) is protected from the series of dry and wet etch steps used to form the cavity. More particularly, the cavity is typically formed selectively between the fuse material and an surrounding insulator, typically silicon nitride. Thus, the typical gate structure (or gate stack) and fuse both include a conductor made up of doped polycrystalline silicon/tungsten silicide encapsulated in a silicon nitride insulator which is selective removed over the fuse to form a cavity for the fuse blown material. This cavity is typically sealed with a plasma deposited silicon dioxide leaving a pocket, i.e.e, the cavity described above, for the blown fuse material. In any event, this later technique requires a separate masking step in the fabrication process.
SUMMARY OF THE INVENTION
In accordance with the invention, a method is provided for forming a fuse for semiconductor integrated circuit. The circuit has an active device. The method includes forming a fuse and an active device in different regions of a semiconductor substrate. A dielectric layer is formed over the fuse and over a contact region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device.
With such method, the same masking step is used to form a cavity for the fuse and contact via holes for the active device.
In accordance with another feature of the invention, a second dielectric layer is formed over the electrically conductive material. A second via hole is formed through the second dielectric layer exposing an underlying portion of a portion of the electrically conductive material deposited onto the contact region of the active device. A metalization layer is formed over the second dielectric layer of a material different from material of the electrically conductive material. A portion of such metalization layer is deposited through the second via onto the exposed underlying portion of the electrically conductive material deposited onto the contact region of the active device.
In accordance with another feature of the invention, a third via hole through the second dielectric over the fuse and over a portion of the metalization layer. An etch is brought into contact with the second dielectric and through the second and third via holes into contact with the exposed portion of the electrically conductive material deposited onto the fuse and into contact with an exposed portion of the metalization layer. The etch selectively removes the exposed portion of the electrically conductive material deposited over the fuse and leaves substantially un-etched the portion of the metalization layer deposited exposed by the second via hole.
In accordance with another feature of the invention, a fill material is deposited into an upper portion of the second via hole over fuse with a bottom portion of such filing material being spaced from the fuse.
In accordance with still another feature of the invention, the electrically conductive material is tungsten and the metalization layer is aluminum.
In accordance with yet another feature of the invention, a semiconductor integrated circuit is provided having a semiconductor substrate with a fuse and an active device disposed in different regions of the semiconductor substrate. The active device has an electrically conductive gate electrode. A dielectric layer is disposed over the fuse and over the gate electrode. The dielectric layer has via holes through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a source/drain contact region of the active device. A first metalization layer having an electrically conductive material is disposed over the dielectric layer and through one of the via holes, such electrically conductive material having a portion thereof disposed on the exposed portion of the source/drain contact region. A second dielectric layer is disposed over the electrically conductive material, such second dielectric material having second via holes through the second dielectric layer, one of such second via holes being disposed over one of the first via holes to expose and underlying portion of the fuse and another one of such second via holes exposing an underlying second portion of the electrically conductive material. A fill material is disposed in the one of the second via holes disposed over the fuse, a bottom portion of such filling material being spaced from the fuse.
REFERENCES:
patent: 5060045 (1991-10-01), Owada et al.
patent: 5844295 (1998-12-01), Tsukude et al.
patent: 5970346 (1999-10-01), Liaw
patent: 5989784 (1999-11-01), Lee et al.
Brintzinger Axel
Tobben Dirk
Weber Stefan J.
Braden, Esq. Stanton C.
Meier Stephen D.
Siemens Aktiengesellschaft
Vockrodt Jeff
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