Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-07-26
2004-02-10
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S218000, C438S275000, C438S583000, C438S592000
Reexamination Certificate
active
06689676
ABSTRACT:
FIELD OF THE INVENTION
This invention is related to a method for making integrated circuits and more particularly to integrated circuits having dual work functions for the control gate electrode.
RELATED ART
In the manufacture of integrated circuits the progress is continuing in the area of faster speed and smaller individual transistor devices. As this continues to occur the commonly used gate (control electrode) of polysilicon is beginning to reach technology levels in which it is inadequate. Its ability to achieve the desired work function for both N and P-channel devices is becoming more and more difficult to achieve while retaining the desired level of conductivity.
One of the difficulties in achieving dual work functions in transistor devices is that the primary technique for achieving this is using two different metal types. The result is very difficult manufacturing processes because the patterned metal etches of metal are difficult to achieve in many cases and also the typical technique requires completely removing one of the metals over the gate oxide that is used for one of the transistor types. For example, if a first deposited metal is going to be used for N-channel transistors, in the locations where there are to be P-channel transistors this first-deposited metal must be completely removed. This is required because the metal that is closest to the channel is what controls the work function. Thus the metal for the N-channels in this case must be completely removed over the P-channel transistors. The result is the etchant that is used to remove this metal comes in contact with the underlying gate dielectric. The gate dielectric then for the P-channel transistors is damaged and may cause reliability issues for transistor gates that are formed over it. Removing the gate damaged gate dielectric and reforming another is generally not practical because of the high heat required to form gate dielectrics of adequate quality for manufacturing. Thus gate dielectrics have become a major issue for this.
Another approach may be to utilize a gate dielectric material that can withstand the etchant materials quite well. In practicality, however, this is very difficult to find. It is very difficult to have a situation in which a gate dielectric receives a metal etchant and is not damaged at all. Further, many metals are fairly difficult to remove, although it is much easier to remove a blanket or wide area of metal than it is to perform an etch requiring a precise edge of a metal such as is required for forming gates.
Thus, there is a need for a way to achieve etching of gate materials that provide the needed dual work functions without requiring difficult patterned metal etches and without causing damage to the gate dielectrics.
REFERENCES:
patent: 6204103 (2001-03-01), Bai et al.
patent: 6261978 (2001-07-01), Chen et al.
patent: 6265258 (2001-07-01), Liang et al.
patent: 2003/0109121 (2003-06-01), Rotondaro
Tavel et al., “Totally Silicided (CoSi2) Polysilicon: A Novel Approach to Very Low-Resistive Gate (-252/ ) Without Metal CMP Nor Etching,” IEEE, 2001, 4 pgs.
Garcia Ricardo
Geren James P.
Koh Al T.
Lii Yeong-Jyh T.
Pham Daniel Thanh-Khac
Clingan, Jr. James L.
Cuneo Kamand
King Robert L.
Motorola Inc.
Sarkar Asok Kumar
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