Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
2003-02-19
2004-06-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C438S678000, C438S675000
Reexamination Certificate
active
06746900
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of forming semiconductor devices, and more particularly to methods of forming semiconductor devices including high-K dielectric layers.
BACKGROUND OF THE INVENTION
As metal oxide semiconductor field effect transistor (MOSFET) feature sizes decrease, the gate oxide thickness of the devices also decreases. This decrease is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions decrease to maintain the proper device scale, and thus device operation. Another factor driving reduction of the gate oxide thickness is the increased transistor drain current realized from a reduced gate dielectric thickness. The transistor drain current is proportional to the amount of charge induced in the transistor channel region by the voltage applied to the gate conductor. The amount of charge induced by a given voltage drop across the gate dielectric (e.g., the gate oxide) is a factor of the capacitance of the gate dielectric.
In order to achieve increased capacitance, gate oxide thicknesses have been decreased to as thin as 10 Å. These extremely thin gate oxides can result in gate oxide breakdown and shifts in threshold voltage of the device from its design specification, likely due to trapped charge that accumulates over time. These concerns have driven an interest in the use of materials that have dielectric constants that are greater than the dielectric constant of silicon oxide, which has a K value of 3.9 Higher K values of 20 or more can be obtained with various transition metal oxides. These “high-K materials” allow high capacitances to be achieved with relatively thick dielectric layers. In this manner, the reliability problems associated with very thin dielectric layers can be avoided while improving transistor performance.
There are fabrication problems associated with forming gate dielectric layers that include high-K materials, particularly when a metal gate is employed. One problem is that high-K materials are generally very difficult to etch. Therefore, there remains a need for a new method of fabricating integrated circuit devices having high-K dielectric layers.
SUMMARY OF THE INVENTION
In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.
REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
patent: 5963818 (1999-10-01), Kao et al.
patent: 6194768 (2001-02-01), Gardner et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6344413 (2002-02-01), Zurcher et al.
patent: 6391752 (2002-05-01), Colinge et al.
patent: 6406945 (2002-06-01), Lee et al.
patent: 6455424 (2002-09-01), McTeer et al.
patent: 6495437 (2002-12-01), Yu
patent: 6573197 (2003-06-01), Callegari et al.
Huang Kuei-Wu
Lei Ming-Ta
Lin Cheng-Chung
Lin Chia-Hui
Lin Yih-Shung
Lindsay Jr. Walter L.
Morris LLP Duane
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd.
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