Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-11-24
2001-07-17
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S631000, C438S612000
Reexamination Certificate
active
06261944
ABSTRACT:
FIELD OF INVENTION
This invention relates, in general, to semiconductor devices and to methods for their fabrication, and more particularly, to passivation layers for semiconductor devices having high-density, multi-level metal interconnects.
BACKGROUND OF THE INVENTION
In order to build faster and more complex integrated circuits, semiconductor device manufacturers have increased the number of components in to the integrated circuits, while reducing the overall size of the circuit. The small circuit size requires multiple overlying metal interconnect layers to electrically connect the vast number of components within the integrated circuit. The multi-level metal interconnects are necessary in order to provide the large quantity of electrical connections necessary to electrically couple the large number of device components to each other, and to electrical circuitry within device packaging.
With the advent of very-large-scale-integration (VLSI) semiconductor technology, multi-level interconnect layers must be fabricated at high density levels. Each metal interconnect layer includes a large number of metal leads arrayed over an interlevel dielectric layer. The individual metal leads are fabricated using high resolution photolithographic and etching methods to have a very small line width. A high packing density of metal leads is obtained by placing the leads very close together, such that a very small line-space pitch is achieved.
In addition to multiple layers of metal, VLSI semiconductor devices also include passivation materials overlying the interconnect layers to protect the underlying circuitry from contamination and from physical damage. Most commonly, multiple passivation layers are employed to relieve stress in the underlying metal and dielectric layers. Excessive stress can cause cracking and void formation in the interconnects resulting in the loss of electrical signals from the affected components within the device. The passivation materials are typically silicon oxides and silicon nitrides. Passivation materials, such as silicon nitride, are commonly used to prevent mobile ions from entering the device structures and causing problems, such as threshold voltage shifting in metal-oxide-semiconductor (MOS) transistors within the device.
As successive layers of conductors and dielectric materials are deposited over previously defined structures, the surface topography can become extremely uneven. The surface roughness is substantially increased when multi-level metal interconnects are used. Also, the requirement for high-density interconnects in VLSI devices further exacerbates the uneven surface topography upon which the passivation layers must be applied. At some point, the surface topography become so uneven that the passivation layers cannot uniformly coat the underlying interconnects. When this happens, voids and open spaces can be created below the passivation layers.
The creation of open spaces within the device is problematic because gases, such as water vapor, can easily collect within the open spaces. In the case of water vapor, water can condense within the open spaces and cause corrosion within the interconnect layers. Most VLSI devices employ a large number of metals, such as copper, copper-aluminum alloy, and the like, which are subject to corrosion upon contact with water. Additionally, gas pressure can build up within the spaces and cause a phenomenon known as “popcorn” cracking in package devices. When this occurs, high pressure gases literally explode out of the package damaging circuit elements in the process. Even in the rare case where a circuit element is not damaged, a leakage path for moisture is created as the outrushing gases create cracks in the various dielectric layers within the package. Once the cracks have been formed, the both moisture and mobile ions can penetrate the passivation layers and contaminate the underlying device components resulting in catastrophic device failure. Accordingly, a need existed for an improved passivation material and process to eliminate the formation of voids and open spaces at the passivation/interconnect interface.
SUMMARY OF THE INVENTION
In practicing the present invention, there is provided a semiconductor device having a high reliability passivation and a method for fabricating the device. The inventive device passivation includes a planarized layer, preferably formed with spin-on-glass (SOG) that is subsequently planarized to form a smooth surface. The planar surface provides a relatively flat surface upon which to further deposit additional passivation layers. Deposition onto a flat surface reduces the formation of voids and open spaces at the interface of the passivation and the underlying, multi-level interconnect layer. By minimizing the formation of voids and open spaces, premature device failure caused by exposure to harsh conditions during assembly and subsequent operation can be dramatically reduced.
In particular, devices fabricated in accordance with the invention show improved package reliability over devices fabricated by prior art methods. In comparison testing, semiconductor devices containing the inventive passivation showed improved reliability during temperate cycling steam pressure testing, thermal, and vibration shock testing and accelerated steam testing.
In one embodiment, the semiconductor device includes a substrate having a plurality of device components thereon. An electrical interconnect layer overlies the plurality of device components, and an insulation layer overlies the interconnect layer. A planarized layer of SOG overlies the insulation layer and at least one additional passivation layer overlies the SOG layer. A method for fabricating the device includes providing a semiconductor substrate having a device layer thereon, and having an interconnect layer overlying the device layer. The interconnect layer is characterized by a highly uneven upper surface. A stress relieving layer is formed to overlie the interconnect layer, and a planarized layer is formed to overlie the stress-relieving layer. Then, a protection layer is formed to overlie the planarized layer, and openings are formed through the protection layer, the planarized layer, and the stress relieving layer. The openings exposed contact surface regions on the interconnect layer to which external device leads can be connected.
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patent: 6027999 (2000-02-01), Wong
Li Xiao-Yu
Mehta Sunil D.
Bowers Charles
Brinks Hofer Gilson & Lione
Lee Hsien-Ming
Vantis Corporation
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