Method for forming a semiconductor device having a fin and...

Details Method for forming a semiconductor device having a fin and... Method for forming a semiconductor device having a fin and...

2006-04-27

2008-10-28

Lee, Calvin (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257S270000

Reexamination Certificate

active

07442590

ABSTRACT:
A method for forming a semiconductor device includes providing a semiconductor layer, forming a passivation layer over the semiconductor layer, wherein the passivation layer has an opening having sidewalls, forming a fin over the semiconductor layer, wherein after forming the passivation layer the fin is within the opening, and forming a portion of a gate within the opening. In one embodiment, a dummy gate is used. In one embodiment, spacers are formed within the opening of the passivation layer. The structure is also discussed.

REFERENCES:
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patent: 6936516 (2005-08-01), Goo et al.
patent: 6951783 (2005-10-01), Mathew et al.
Doris, B. et al.; “Ultra-Thin SOI Replacement Gate CMOS with ALD TaN / High-k Gate Stack”; VLSI Technical Symposium; 2005; pp. 101-102; IEEE.
Mathew, L. et al.; “Multiple Independent Gate Field Effect Transistor (MIGFET)—Multi Fin RF Mixer Architecture, Three Independent Gates (MIGFET-T) Operations and Temperature Characteristics”; 2005 Symposium on VLSI Technology 2005 Digest of Technical Papers; Jun. 14-16, 2005; pp. 200-201.
Chang, C.P. et al.; “SALVO Process for Sub-50 nm Low-VT Replacement Gate CMOS with KrF Lithography”; IEDM; 2000; pp. 53-56.
U.S. Appl. No. 11/339,953, filed Jan. 26, 2006.

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