Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-02-07
2001-11-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S289000, C438S299000, C438S303000, C438S305000, C438S592000, C438S652000
Reexamination Certificate
active
06319807
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor devices, and more particularly to, a method for forming a Metal-Oxide-Semiconductor devices having reverse-offset spacer.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductors, become highly integrated, the area occupied by the devices shrinks, as well as the design rule.
A cross-sectional view of a Metal-Oxide-semiconductor device of the know prior art is illustrated in
FIG. 1. A
semiconductor substrate
20
is a silicon substrate. The semiconductor substrate includes shallow trench isolation
22
, and which collocates to form a gate oxide layer
24
and a gate
26
on the surface of the semiconductor substrate
20
. Lightly doping drain regions
30
formed in the semiconductor substrate
20
after an ion implantation is performed, and then an oxide spacer
32
are formed on the sidewall of gate
26
. Then, source/drain regions
28
are formed in the substrate
20
, so as to perform heavily doping of ion implantation. Obviously, the gate width is fixed and is correspondent with effective channel length. Moreover, a small size of the semiconductor device is fabricated for producing a high speed semiconductor device. Thus, the effective channel length of the gate has to be reduced, but the length of the Metal-Oxide-Semiconductor device can not be unlimitedly reduced, because the length of channel is reduced to result in variable derivational problem. Hence, this phenomenon is called “Short Channel Effect”.
As the device continuously shrinks to sub-quarter micron regime, since poly gate lithography is the key limitation, it is very difficult to keep good performance on Poly gate CD (Critical Dimension) control. By the way, Ti or Co silicide will be more difficult to form on sub-quarter micron, due to the line-width effect and shallow junction issue.
And yet, in accompanying with the shrinkage of devices, the thickness of the gate can be not too thick from the conventional process of the small size. If the thickness of the gate is too thick, it will result in the source/drain junction issue. Thicker silicon substrate is consumed at the source/drain region, when silicide is formed by means of using rapid thermal processing. Hence, results in shallower junctions. In order to avoid the formation of junctions leakage, the thickness of silicide layer at the source/drain region must be thinner enough as devices shrink in size.
When the size of the element is reduced, the surface joint in the source/drain must be shallow to match up with, so the short channel effect could be avoided. Moreover, the size of the gate is fixed within the conventional process, due to the overlapped channel can not be reduced. Herein, overlapped channel was formed by way of the source/drain extension at high temperature.
In deep sub-micron device fabrication, the process treats the salicide on the source/drain that is important and comprehensive application. The above can be accomplished by either using simple silicidation of source/drain. It will be difficult to deal with the salicide on the gate, while the size of the gate is considerably small.
In accordance with the above description, a new and improved method for fabricating the Metal-Oxide-Semiconductor device is therefore necessary, so as to raise the yield and quality of the follow-up process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating Metal-Oxide-Semiconductor devices that substantially overcomes drawbacks of above mentioned problems arised from the conventional methods.
Accordingly, it is an object of the present invention to provide a method for fabricating Metal-Oxide-Semiconductor devices, having a reverse offset-spacer, so as to form small size high speed and high performance elements or CPU (central processing unit). By means of forming the reverse offset-spacer for reducing the Poly-CD (critical dimension), an overlapped length can be controlled with an appropriate structure. Due to combination with local punch-through implantation, junction capacitance can be significantly reduced.
Another object of the present invention is to reduce effective channel length only by way of forming the reverse offset spacer; Hence, the limitation of the lithography process can be improved by the reverse offset spacer. The effective poly line-width can be increased by salicidation herein; Thus, the narrow line-width effect of the salicide can be reduced by this structure.
A further object of the present invention is to form the thinner silicide at source/drain regions with this structure which has reverse offset-spacer; Thus, good ultra-shallow junction integrity can be obtained.
In accordance with the present invention, a method for forming semiconductor devices is disclosed. In one embodiment of the present invention, a semiconductor substrate having shallow trench isolation (STI) regions is provided. Firstly, a silicon nitride films is deposited on the semiconductor substrate that comprises shallow trench isolation region. Thus, a dummy gate can be formed on the substrate by means of defined process. And then a silicon dioxide films is deposited again on the substrate after carried out the lightly doped drain. Then, the oxide spacer is formed on the wall-side of the dummy gate with appropriate anisotropic etching. Moreover, the heavily doped drain process is carried out to form the source/drain. The final stage would be an annealing process. After source/drain extension formation, oxide spacer and source/drain deep junction are formed, and thinner salicide is formed to keep good junction integrity. Then, a thick films of the ILD (Inter Layer Dielectric) layer is deposited followed by post ILD CMP (Chemical Mechanical Polishing) stop layer on this dummy gate. With appropriate wet etching in a wet phosphoric acid solution, this dummy gate can be removed. After local punch-through implantation, reverse offset spacer was formed. Polysilicon is deposited followed by polysilicon CMP stop on the thickness of the dummy gate, thus, a reverse polysilicon can be obtained. Final, thick Ti-salicidation is carried out.
REFERENCES:
patent: 5856225 (1999-01-01), Lee et al.
patent: 6087208 (2000-07-01), Krivokapic et al.
Lin Tony
Yeh Wen-Kuan
Bowers Charles
Chen Jack
Powell Goldstein Frazer & Murphy LLP
United Microelectronics Corp.
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