Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1999-06-17
2000-08-22
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438620, 438621, H01L 2176
Patent
active
061071870
ABSTRACT:
An opening (24) is formed in a substrate (20). A first layer (30) is formed over the substrate (20) and the feature opening (24). A second layer (40) is formed over the first layer (30) and then the second layer is removed until exposing portions (50) of the first layer (30). The exposed portions (50) of the first layer (30) are then optionally removed using remaining portions (52) of the second layer (40) as a patterning mask to form a cavity (60) in the first layer (30). The remaining portions of the second layer (52) are then removed and the first layer (30) is polished to form a semiconductor device structure (80). In one embodiment, the first layer is dielectric layer, and in an alternative embodiment, the first layer is a conductive layer.
REFERENCES:
patent: 5173439 (1992-12-01), Dash et al.
patent: 5719073 (1998-02-01), Shaw et al.
B. Davari et al., A New Planarization Technique, Using a Combination of Rie and Chemical Mechanical Polish (CMP), 1989 IEEE, pp. 3.41-3.44.
S.S. Cooperman et al., "Optimization of a Shallow Trench Isolation Process for Improved Planarization", J. Electrochem. Soc., vol. 142, No. 9, Sep. 1995, pp. 3181-3185.
Karzhavin Yuri Y.
Kelly Patrick Michael
Lao Keith Q.
Bowers Charles
Kilday Lisa
Motorola Inc.
Rodriguez Robert A.
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