Method for forming a semiconductor device

Details Method for forming a semiconductor device Method for forming a semiconductor device

1998-02-12

2002-02-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S240000, C438S387000

Reexamination Certificate

active

06344413

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor devices, and more particularly, to a scaled down memory capacitor which enables high density integrated circuit manufacturing.
BACKGROUND OF THE INVENTION
Semiconductor devices are requiring larger and larger memory densities. A dynamic-random-access memory (DRAM) cell is an example of one type of memory.
FIG. 1
includes a schematic diagram of a DRAM memory cell
25
that includes a transistor
5
and a capacitor
10
. A source/drain region of transistor
5
is electrically connected to a bit line
20
, and the other source/drain region of transistor
5
is electrically connected to one of the electrodes of capacitor
10
. The gate electrode of transistor
5
is electrically connected to a word line
15
. The other electrode of capacitor
10
is electrically connected to VSS or a substantially constant potential (not shown). A one-transistor, one-capacitor ferroelectric random-access memory (FeRAM) is similar except that the electrode of capacitor
10
is electrically connected to a drive line instead of VSS or a substantially constant potential.
When the memory cell
25
is shrunk, capacitance of capacitor
10
must be kept high enough to allow proper sensing of the memory cell
25
. As the processing technology is taken below 0.50 &mgr;m, difficulties arise.
Capacitance is given by the formula:
C
=
k
·
ϵ
0
·
A
d
Silicon dioxide is a common type of capacitor dielectric. However, its thickness cannot be taken lower than 40 Å because it cannot be reproducibly made in a manufacturing environment without defects. Additionally, reduced thickness increases potential leakage current, which effects the time necessary to refresh the memory cell. Nontraditional high dielectric constant materials having a dielectric constant higher than 10 typically have process compatibility issues. Polysilicon electrodes may not be used because many of the nontraditional high dielectric constant materials may adversely interact with those materials.
Still another attempt to increase capacitance is to increase the capacitor area. To achieve higher capacitor area without occupying additional substrate area, capacitors are including a vertical component as seen in FIG.
2
. Memory cell
25
includes transistor
5
and capacitor
10
that are illustrated with dashed lines. Transistor
5
is electrically connected to capacitor
10
by contact plug
26
that has a width of “f.” The capacitor includes lower electrode
30
having a “U” shape, a capacitor dielectric layer
40
, and an upper electrode
35
. The capacitor
10
has side extensions that are oriented in the Z direction as shown in FIG.
2
. The Z-direction orientation complicates the manufacturing of memory cell
25
. The films that make up the capacitor
10
may need to be conformally deposited and the subsequent interlevel dielectric layer (not shown) deposited and planarized without adversely affecting the upper electrode
35
or forming voids.


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