Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-04-07
2002-04-16
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S681000, C438S683000, C438S685000, C438S643000
Reexamination Certificate
active
06372643
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to processes for forming selective contacts and metal silicide interconnects on semiconductor devices. In particular, the present invention relates to processes wherein a local interconnect, which acts as a barrier layer, is deposited prior to forming an electrical contact, via, or other electrically conductive structure that forms a junction with an active device region. Specifically, the local interconnect and selective contact are formed in situ (i.e., in the same chamber without removing the semiconductor device therefrom between deposition of the interconnect and the selective contact).
2. Background of Related Art
The isolated active regions of a semiconductor device are typically covered with an insulative, or dielectric layer, and are only exposed to the active surface of the semiconductor device by openings through the insulative layer, which are referred to as contact openings, or “contacts” for simplicity. In order for the semiconductor device to function, electrical connections must be established between the various active device regions. Conductive paths or lines are fabricated on the active surface of the semiconductor device to electrically interconnect the active regions of the semiconductor device.
The interconnection of many electrically conductive materials to a semiconductor substrate, however, generates a great deal of contact resistance. In turn, the resistance of such contacts tends to convert some of the electrical energy transmitted therethrough into heat. With the ever-increasing density of integrated circuits carried on semiconductor devices and the ever-increasing size of semiconductor devices, such high levels of contact resistance necessitate increased power input and an increase in the operating temperatures of state-of-the-art semiconductor devices. Consequently, it has become necessary to reduce the contact resistance at the junction of the contact and the conductive path or line that is electrically connected thereto. A principal way of reducing contact resistance includes the formation of a metal silicide layer over the contact prior to the fabrication of the conductive line or path that will be electrically connected thereto. Such metal silicide layers are commonly referred to as selective contacts. Titanium silicide (TiSi
x
, wherein x is predominantly equal to 2) is a refractory metal silicide that is commonly employed as a selective contact in order to reduce contact resistance. The formation of metal silicide selective contacts typically includes the deposition of a thin layer of titanium and titanium nitride onto the semiconductor device, including the semiconductor substrate of the active device regions that are exposed through the contact openings. A high temperature anneal, such as the type that is known in the art as a rapid thermal anneal (RTA), is then employed, causing the titanium and titanium nitride to react with the semiconductor substrate to form a silicide (i.e., TiSi
x
) selective contact. This process is said to be self-aligned since the TiSi
x
forms only over semiconductor substrate (e.g., silicon and polysilicon) regions. The remaining titanium and titanium nitride which overlies the selective contact acts as an interconnect, or a barrier layer, and prevents the diffusion of silicon and silicide into any electrically conductive material that is subsequently deposited thereover. Everywhere else, the applied titanium film overlies an insulative, substantially non-reactive field oxide layer, and may subsequently be removed.
An exemplary barrier layer is formed of titanium nitride, which is typically blanket deposited over a semiconductor device by the following chemical reaction:
TiCl
4
+NH
3
→TiN↓.
Upon subjecting the semiconductor device to temperatures of about 500° C. or higher (e.g., by a rapid thermal anneal), the deposited titanium reacts with the silicon substrate to form a silicide layer. The silicide layer formed by this process, however, often creates an undesirably thick selective contact junction between the semiconductor substrate beneath and the interconnect above.
Another such process, which is directed to the deposition of metal directly upon the silicon substrate to form a metal silicide film thereon in order to fabricate selective contacts and local interconnects, is disclosed in U.S. Pat. No. 5,416,045 (the “'045 patent”), which issued to Ralph E. Kauffman et al. on May 16, 1995. The process that is disclosed in the '045 patent utilizes nitrogen gas (N
2
) to facilitate titanium nitride deposition at temperatures of about 500° C. or less by slowing the reaction rate, comparative to other similar processes, to improve step coverage of the titanium nitride layer. The titanium nitride layer is subsequently annealed to the substrate by known rapid thermal anneal techniques in order to form a metal silicide selective contact between the substrate and the titanium nitride layer.
Although the process of the '045 patent reduces problems associated with poor step coverage, it is somewhat undesirable from the standpoint that the titanium nitride layer may consume excessive amounts of the underlying silicon during the rapid thermal anneal, and, in turn, form deeper silicide junctions (i.e., thicker than selective contacts) than are desirable in many electrically conductive structures.
Several other prior art processes include the direct deposition of metal suicides upon the silicon substrate. The following United States Patents disclose exemplary metal silicide deposition techniques: U.S. Pat. No. 5,376,405, issued to Trung T. Doan et al. on Dec. 27, 1994; U.S. Pat. No. 5,278,100, issued to Trung T. Doan et al. on Jan. 11, 1994; and U.S. Pat. No. 5,240,739, issued to Trung T. Doan et al. on Aug. 31, 1993. None of the foregoing patents, however, discuss the subsequent in situ deposition of an interconnect over the metal silicide selective contact.
When a silicide layer is deposited directly onto the active device regions of the semiconductor device that are exposed through contact openings, since many desirable electrically conductive contact opening filling materials, such as tungsten (W), adhere poorly to selective contact materials such as TiSi
x
, and further because the silicon and many selective contact materials tend to diffuse into many types of contact opening filling materials, an intervening interconnect is often desirable to promote adherence of the contact opening filling material to the underlying substrate. As noted above, interconnects that are manufactured from materials such as titanium nitride provide the additional advantage of inhibiting the diffusion of silicon and silicide into the contact opening filling material, and are therefore typically referred to as barrier layers.
Many interconnect fabrication processes, however, are performed in a separate reaction chamber than that in which the silicide deposition was performed, requiring that the semiconductor devices be transferred between the silicide deposition and the barrier layer deposition. Consequently, the fabrication time, amount of equipment required, and equipment down time are increased, which drives fabrication costs higher.
Accordingly, Applicants have recognized a need for a process of forming conductive structures upon semiconductor substrates, wherein a selective contact of desirable thickness is deposited onto semiconductor substrate material exposed through a contact opening, and an interconnect is subsequently deposited onto the selective contact in situ.
SUMMARY OF THE INVENTION
The present invention addresses the above-identified needs.
The process of the present invention includes the fabrication of selective contacts and local interconnects over the exposed regions of semiconductor substrate (e.g., active device regions) of semiconductor devices. The inventive process includes depositing a selective contact, such as a thin metal silicide layer, which is also referred to as a salicide layer, onto a semiconduc
Hill Christopher W.
Li Weimin
Sandhu Gurtej S.
Eaton Kurt
Fahmy Wael
Micro)n Technology, Inc.
TraskBritt
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