Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-02-17
2001-06-12
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S510000, C438S526000
Reexamination Certificate
active
06245649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of semiconductor devices, and, more particularly, to a method for forming a retrograde impurity profile in a semiconducting material.
2. Description of the Related Art
Ion implantation processes are widely used in the fabrication of very large scale integration (VLSI) and ultra large scale integration (ULSI) integrated circuit devices to introduce a desired quantity of dopant atoms into a target substrate material. For example, ion implantation is a commonly used process for introducing impurities, e.g., dopant materials, into the surface of a semiconducting substrate in order to modulate the conductive properties of the semiconducting substrate.
It is generally desired that a dopant material be implanted to some depth within a semiconducting substrate that is being prepared for device fabrication rather than having the dopant concentrated at or near only the surface of the semiconducting substrate. In one approach for introducing dopant impurities into a semiconducting substrate, a suitable dopant is introduced into the surface of the substrate and diffused to a desired depth by heating the substrate. Under such conditions, the diffusion of the dopant material occurs laterally as well as vertically, resulting in lateral spreading of the dopant within the substrate. Such lateral spreading of the dopant material has the undesired effect of reducing the packing density of the implanted material in the semiconducting substrate, which can adversely influence the properties of semiconducting devices subsequently fabricated on the surface of the substrate. Moreover, as illustrated in diffused impurity profile
6
of
FIG. 1
, although dopant can be diffused to some depth within the semiconducting substate, the dopant concentration is invariably highest at the surface of the substrate and decreases with increasing depth.
For many applications, it is desired that the peak concentration of the dopant material occurs at some depth under the surface of the substrate rather than at the substrate surface. This is generally referred to as a retrograde impurity profile. Retrograde impurity profiles may be formed using high-energy ion implantation processes, which allow for improved impurity depth control and reduced spreading compared with diffusion techniques. In an illustrative retrograde impurity profile
8
, as represented in
FIG. 1
, the concentration Y of the implanted dopant material at depth X is higher than the concentration Z observed at depth X for diffused impurity profile
6
. Thus, in contrast to diffused impurity profile
6
, the concentration of the dopant material for a retrograde impurity profile
8
is highest at some depth within the substrate, rather than at the surface, and decreases as it approaches the substrate surface. Retrograde impurity profiles in a semiconducting substrate are particularly useful in integrated circuit manufacturing, for example, to form n-well and p-well regions in complementary metal oxide semiconductor (CMOS) transistors and to produce buried collector regions in bipolar transistors. Some of the advantages provided by retrograde impurity profiles in the manufacture of CMOS and other devices include reduced susceptibility to vertical punchthrough and improved protection from latchup.
In prior art methods for forming retrograde impurity profiles, dopant ions are commonly directed at a layer of material overlying the surface of the semiconducting substrate rather than being implanted directly into the substrate. As a result, the ions contact and penetrate this surface layer before they penetrate the semiconducting substrate. The surface layer may serve as a protective screen against contamination by metals or other impurities during the implant. Moreover, the layer may also be important in reducing the extent of ion channeling in the substrate by randomizing the direction of the ions as they enter the substrate lattice. This surface layer typically is referred to as a “sacrificial” layer because it is generally removed at some point after the implantation process.
The thickness of sacrificial surface layers used in prior processes for forming retrograde impurity profiles in semiconducting substrates has been generally greater than 200 Å. However, sacrificial layers having thicknesses greater than 200 Å may be associated with less than desirable dopant depth control and spreading, which can adversely effect the performance of transistors fabricated thereafter above the surface of the semiconducting substrate.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for forming a retrograde impurity profile in a semiconducting substrate. The method involves first forming a sacrificial layer comprising an oxide, nitride, or other like material, on the surface of a semiconducting substrate. The sacrificial layer has a thickness in the range of about 10 Å to about 150 Å, and may be formed by any of a variety of techniques, including thermal oxidation, deposition, and the like. Thereafter, an ion implantation process is performed in which dopant impurity ions, such as arsenic, indium, gallium, antimony, or other like ions, are directed at the surface of the sacrificial layer. The impurity ions will typically be directed at the sacrificial layer using an implantation energy in the range of about 50 Kev to about 200 Kev, and having a dose in the range of about 1×10
12
ions/cm
2
to about 5×10
13
ions/cm
2
. By practice of this invention, a steep retrograde impurity profile is formed in the semiconducting substrate. Integrated circuit devices fabricated on the surface of the semiconducting substrate will have improved performance characteristics as a result of the steep retrograde impurity profile formed therein.
REFERENCES:
patent: 4463493 (1984-08-01), Momose
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4965648 (1990-10-01), Yang et al.
patent: 5079177 (1992-01-01), Lage et al.
patent: 5264394 (1993-11-01), Ruckman et al.
patent: 5266510 (1993-11-01), Lee
patent: 5292671 (1994-03-01), Odanaka
patent: 5349225 (1994-09-01), Redwine
patent: 5409848 (1995-04-01), Han et al.
patent: 5547882 (1996-08-01), Juang et al.
patent: 5565377 (1996-10-01), Weiner et al.
patent: 5637512 (1997-06-01), Miyasaka et al.
patent: 5656844 (1997-08-01), Klein et al.
patent: 5770485 (1998-06-01), Gardner et al.
patent: 5827763 (1998-10-01), Gardner et al.
patent: 5837597 (1998-11-01), Saito
patent: 5864163 (1999-01-01), Chou et al.
patent: 5866458 (1999-02-01), Lee
patent: 5989963 (1999-11-01), Luning et al.
Shahidi et al., “Indium Channel Implant for Improved Short-Channel Behavior of Submicrometer MOSFETs,”IEEE Electron Device Letters, 14(8):409-11, 1993.
Bouillon et al., “Re-examination of Indium implantation for a low power 0.1 &mgr;m technology,”Int'l Electron Devices Meeting Technical Digest, IEDM 95, pp. 897-900, 1995.
Buller James F.
Cheek Jon D.
Fulford H. Jim
Kadosh Daniel
Wristers Derick J.
Advanced Micro Devices , Inc.
Le Vu A.
Pyonin Adam
Williams Morgan & Amerson P.C.
LandOfFree
Method for forming a retrograde impurity profile does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a retrograde impurity profile, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a retrograde impurity profile will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2521441