Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2002-02-26
2003-08-26
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
C438S527000
Reexamination Certificate
active
06610585
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing; more specifically, it relates to a method for forming a retrograde ion implant.
BACKGROUND OF THE INVENTION
Modern semiconductor devices such as N channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs) require careful tailoring of the dopant concentration profile in the channel region of the device in order to control voltage (V
T
), off currents (I
OFF
) and short channel effects (SCE). For an NFET, the channel is formed by control of the P-well dopant profile concentration. For a PFET, the channel is formed by control of the N-well dopant profile concentration. Control of the respective N or P-well profile is accomplished by performing at least one low-voltage and low-dose shallow ion implant and at least one high-voltage and high-dose ion retrograde implant, both of the same dopant type. A shallow implant is one in which the implanted species remain relatively close to the silicon surface. A retrograde implant is one in which the highest dopant concentration of the implanted species occurs a distance below the silicon surface. The channel/well profile tailoring ion implant processes may be best understood by reference to
FIGS. 1A and 1B
.
FIGS. 1A and 1B
are partial cross-sectional views illustrating a related art method of forming a P-well or an N-well. In
FIG. 1A
, formed in a substrate
100
is shallow trench isolation (STI)
105
. Formed on a top surface
110
of silicon substrate
100
is a thin oxide layer
115
. Formed on a top surface
120
of STI
105
is a photoresist image
125
. A low-voltage and low-dose ion implantation of ion species “X,” where “X” represents boron for a P-well or phosphorus for an N-well, is performed. Ions
130
A pass through thin oxide layer
115
and penetrate into substrate
100
forming a shallow portion
135
of well
140
. Ions
130
B striking photoresist image
125
are absorbed by photoresist image
125
. Ions
130
C, striking near sidewall
145
of photoresist image
125
are deflected by atoms in the photoresist but image lack sufficient energy to pass through the sidewall of the photoresist image.
In
FIG. 1B
, a high-voltage and high-dose ion implantation of ion species “X,” where “X” represents boron or for a P-well or phosphorus for an N-well, is performed. Ions
150
A pass through thin oxide layer
115
and penetrate into substrate
100
forming a deep portion
155
of well
135
. Ions
150
B striking photoresist image
125
are absorbed by the photoresist image. Ions
150
C, striking near sidewall
145
of photoresist image
125
penetrate into the photoresist image, are deflected by atoms in photoresist image
125
, and have sufficient energy to escape through sidewall
145
, pass through thin oxide layer
115
and penetrate into an edge region
160
of well
140
. Edge region
160
extends a distance “W” into well
140
measured from resist sidewall
145
. Edge region
160
extends a depth “D” measured from a top surface
165
of thin oxide layer
115
. Obviously P-wells or N-wells away from photoresist image
125
are not effected and do not have edge regions, “D” can range from about near zero to 0.5 microns and “W” can range from about near zero to 1.2 microns. The V
T
of NFETs and PFETs devices fabricated in wells adjacent to photoresist image
125
can differ from the V
T
of NFETs and PFETs fabricated in wells away from (non-adjacent) by as much as about 20 to 120 millivolts. The concentration of dopant in the shallow portion
135
of well
140
in edge region
160
can be ten times the concentration of dopant in the rest of shallow portion
135
of well
140
.
Since devices fabricated away from edge region
160
or in wells away from a resist sidewall, which will not have an edge region, their V
T
will not be increased. Integrated circuits fabricated from a mix of edge and non-edge NFETs and PFETs will have some slow devices and some fast devices. Integrated circuits fabricated from a mix of edge and non-edge NFETs and PFETs and will often exhibit asymmetric behavior.
Therefore, what is needed is a method of forming retrograde ion implants that dose not cause increased dopant concentrations in edge regions of P-wells and N-wells.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method of ion implantation comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.
A second aspect of the present invention is a method of ion implantation comprising: providing a substrate; forming a blocking layer on the substrate; forming a masking image having a sidewall on the blocking layer; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.
A third aspect of the present invention is a method of ion implantation comprising: providing a substrate; forming a first blocking layer on the substrate and a second blocking layer on the first blocking layer; forming a masking image having a sidewall on the second blocking layer; and performing a retrograde ion implant through the first and second blocking layer into the substrate, wherein the second or first and second blocking layers substantially blocks ions scattered at the sidewall of the masking layer.
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Brown Jeffrey S.
Colwill Bryant C.
Hook Terence B.
Hoyniak Dennis
International Business Machines - Corporation
Mulpuri Savitri
Sabo William D.
Schmeiser Olsen & Watts
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