Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-11-13
2003-08-05
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S787000, C438S780000, C438S781000, C438S782000
Reexamination Certificate
active
06602801
ABSTRACT:
FIELD OF THE INVENTION
The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a method for forming a nanoporous material suited for use as an intermetal dielectric (IMD) and/or interlayer dielectric (ILD) material.
BACKGROUND ART
As semiconductor geometries continue to become smaller and smaller, new difficulties arise in the fabrication of semiconductor devices. As one example, with progressively finer design rules, a problem has arisen due to capacitance between adjacent metal layers (i.e. interlayer capacitance). That is, as devices shrink in size, adjacent layers are spaced more closely together. Such a condition results in a deleterious increase in interlayer capacitance which adversely affects operation of finer design rule-based semiconductor devices. A similar problem exists due to the reduced distance between adjacent metal lines. Specifically, under some circumstances, unwanted effects such as cross-talk and various other RC (resistance/capacitance) effects between closely spaced metal lines negatively affect the operation of the semiconductor devices.
It is well known that the dielectric constant for a conventional interlayer dielectric material such as, for example, CVD-deposited silicon dioxide is around 3.9. However, according to the SIA (Semiconductor Industry Association) roadmap, by the year 2005 ultra-low dielectric constant materials (i.e. materials with a dielectric constant of 2.0 or less) will be required for use in 100 nanometer generation integrated circuits. Therefore, it is increasingly important to reduce the dielectric constant of an interlayer and/or intermetal insulating material.
It is generally agreed that only porous materials can achieve the desired reduced dielectric constants (i.e. dielectric constant of less than 2.0). One conventional method for creating a porous dielectric material is to positively form voids within the material. In one prior art approach, small particles within the dielectric are subjected to an etching process. However, such a prior art approach is not particularly cost effective, is not time effective, and does not readily produce desired results.
Furthermore, in order to achieve widespread acceptance, and to ensure affordability, any method of forming a low dielectric constant nanoporous material, which overcomes the above-listed drawbacks, should be compatible with existing semiconductor fabrication processes.
Thus, a need exists for a method for forming a nanoporous material for reducing interlayer capacitance and reducing RC effects between neighboring metal lines. Yet another need exists for a method for forming a nanoporous material which meets the above need and which does not require etching of small particles. Still another need exists for a method for forming a nanoporous material wherein the method meets all of the above-listed needs and wherein the method is compatible with existing semiconductor fabrication processes.
SUMMARY OF INVENTION
The present invention provides a method for forming a nanoporous material for reducing interlayer capacitance and reducing RC effects between neighboring metal lines. The present invention further provides a method for forming a nanoporous material which achieves the above accomplishment and which does not require etching of small particles. The present invention further provides a method for forming a nanoporous material wherein the method achieves the above-listed accomplishments and wherein the method is compatible with existing semiconductor fabrication processes.
In one embodiment of the present invention, the present method comprises the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.
In another embodiment, the present invention includes the steps of the above-described embodiment, and further includes the step of subjecting the solution, after application to the surface, to a thermal process. In this embodiment, the thermal process includes a baking stage, a first thermal treatment stage, and a second thermal treatment stage. In the present embodiment, the baking stage is performed to drive out the solvent. Also, the first thermal treatment stage is performed to induce curing of the low dielectric constant material. Furthermore, the second thermal treatment stage is performed to induce decomposition of the pore generator material such that nanopores are formed within the low dielectric constant material.
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Chooi Simon
Kong Siew Yong
Sarkar Gautam
See Alex
Chartered Semiconductor Manufacturing Ltd.
Dang Trung
Wagner , Murabito & Hao LLP
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