Method for forming a polysilicon layer in a polycide process...

Details Method for forming a polysilicon layer in a polycide process... Method for forming a polysilicon layer in a polycide process...

1999-01-12

2001-02-20

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S586000, C438S655000

Reexamination Certificate

active

06191019

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to a method for forming a polysilicon layer in a polycide layer, and more particularly, relates to a method for forming a polysilicon layer in fabricating a polycide layer of a gate electrode of a transistor.
BACKGROUND OF THE INVENTION
As semiconductor technology progresses, more devices must be implemented in a single chip. This requires that the line width of a semiconductor device become smaller. In the prior art, when a transistor is to be fabricated (see FIG.
1
), a single crystal silicon substrate
100
with a crystallographic orientation of <100> is used. A thick field oxide (FOX) region is formed to provide isolation between devices on the silicon substrate. Sequentially, a first dielectric layer
102
is formed on the top surface of the substrate
100
to serve as the gate oxide for the MOSFET. The first dielectric layer
102
is typically a silicon dioxide layer.
The next step is to form a polysilicon layer
103
and a tungsten silicide layer
104
over the gate oxide. Next, the standard photolithography and etching steps are used to form a gate structure of the MOSFET (see FIG.
2
). After the gate is formed, the photoresist pattern
113
is removed and an ion implantation step is used to define the source and drain electrodes of the transistor.
Referring to
FIG. 3
, ion implantation
120
is performed using the gate as the mask. The ion penetrates the first dielectric layer
102
to form a first doped region
122
in the substrate
100
. The first doped region
122
is formed by the phosphorous dose of approximately 10
13
ions/cm
2
. Then an annealing step is used after the implantation step to repair the damaged lattice.
The photoresist pattern
113
is then stripped. A dielectric layer
130
as shown in
FIG. 4
is then formed. Turning to
FIG. 5
, the dielectric layer
130
is then anisotropically etched to form sidewall spacers
140
.
Referring to
FIG. 6
, to form a second doped region
161
, a second ion implantation
160
is performed. The gate serves as a mask when the second ion implantation
160
is processed. The second doped region
161
can be formed by arsenic ion implantation with a dosage of approximately 5×10
15
ions/cm
2
.
Referring to
FIG. 7
, a BPSG layer
165
is formed on the wafer. Then a masking and etching step is used to etch the BPSG layer
165
to form the contact hole
167
.
Finally, referring to
FIG. 8
, a metal layer
170
is patterned into the contact holes and a passivation layer
175
is formed. The passivation layer mentioned above is typically composed of silicon nitride and PSG.
In the foregoing steps, all of the thermal processes, such as annealing, have an effect on the gate layers
103
and
104
. The resistance of the tungsten silicide layer
104
is high (about 750-850 &mgr;m-cm) when the etching process forming the gate is performed. Therefore, an annealing process is performed to reduce the resistance of the gate tungsten silicide layer
104
to below 70 &mgr;m-cm. However, the annealing process mentioned above results in the diffusion of silicon atoms from the polysilicon layer
103
to the gate tungsten silicide layer
104
. This causes a void in the gate polysilicon layer
103
.
The present invention provides a method for forming a transistor as well as preventing void formation in a gate electrode of said transistor.
SUMMARY OF THE INVENTION
A method for preventing void formation in a gate of a transistor formed in a substrate is disclosed. The method comprises: forming a gate oxide layer on said substrate; forming a polysilicon layer on said gate oxide layer; performing an ion implantation on said polysilicon layer, said ion implantation performed with a power in the range of about about 30 or more than 30 KeV and a dosage of about 10
15
or more than 10
15
atoms/cm
2
; and forming a silicide layer on said polysilicon layer.
Further, a method for forming a transistor on a substrate is disclosed. The method comprises: forming a gate oxide layer on said substrate; forming a polysilicon layer on said gate oxide layer; performing a first ion implantation on said polysilicon layer; forming a silicide layer on said polysilicon layer; patterning and etching said polysilicon layer and said silicide layer to form a gate structure; annealing said polysilicon layer and said silicide layer; performing a second ion implantation to form a first doped region in said substrate; forming a spacer on the side wall of said gate structure to form a gate electrode; performing a third ion implantation to form a second doped region in said substrate; forming a dielectric layer over said gate electrode and said first and second doped region; patterning said dielectric layer to expose said second doped region; forming a conductive layer over said dielectric layer and said second doped region; patterning and etching said conductive layer to be coupled to said second doped region; and forming a passivation layer on said conductive layer and said dielectric layer.


REFERENCES:
patent: 4786611 (1988-11-01), Pfiester
patent: 5256894 (1993-10-01), Shino
patent: 5272099 (1993-12-01), Chou et al.
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5827762 (1998-10-01), Bashir et al.
patent: 5837601 (1998-11-01), Matsumoto
patent: 5924001 (1999-07-01), Yang et al.
patent: 5989950 (1999-11-01), Wu

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