Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-12-30
2001-04-24
Nelms, David (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S305000, C438S586000, 43
Reexamination Certificate
active
06221746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to poly gate fabrication, and more particularly to a method for forming the metal silicide layer within poly gate.
2. Description of the Prior Art
Polysilicon is generally used to form the conductive part of metal-oxide-semiconductor (MOS), but the resistance value of polysilicon is too high to use even it is doped with impurity. Therefore, metal silicide is generally formed on polysilicon and used to decrease the resistance value of conductive part of MOS and then the operation of gate is improved. In addition, if there is any thermal processes in the following process of gate fabrication, phase transformation of the metal silicide may occur and the structure of gate is changed. No matter how, the ratio of metal to silicon is variable, which depends on the chemical reaction and the chamber condition, etc. Thus, the phase transformation temperature is sensitive depending on the ratio of metal to silicon.
The known process of poly gate formation comprises following steps. First, as shown in
FIG. 1A
, forming a dielectric layer
110
over a substrate and then forming a polysilicon layer
112
on dielectric layer
110
. A metal silicide layer
114
is then formed on the polysilicon layer
112
, where the popular metal silicide is tungsten silicide. Afterwards, as shown in
FIG. 1B
, a passivation layer
120
is capped over the metal silicide layer
112
, since the capping process is a high temperature process so the structure of metal silicide is transformed to a new metal silicide structure
116
. Furthermore, an anti-reflection layer
118
could be formed over metal silicide layer
116
before forming the passivation layer
120
. Subsequently, conventional standard photolithography method is used to form the primary structure of poly gate as
FIG. 1C
shows. After the etching process is over, gate etch anneal process is used to restore the etching damage on the surface and sidewall oxide
124
is formed on the sidewall to protect the poly gate as shown in FIG.
1
D. It is obvious that because both gate etch anneal and sidewall oxide formation are high temperature process, the structure of metal silicide
116
maybe change during these process and another metal silicide structure
122
is formed. The metal silicide structure
122
replaces the previous metal silicide structure
116
and induces peaks, dips and nodules on the surface of poly gate. In other words, the surface of poly gate is roughened and those extrusions often cause some disadvantages. For example, when a poly gate is close to other gate then these extrusions in different poly gate maybe is too close so current is conducted from one poly gate to another poly gate, this is so-called gate to gate short.
By the way, it is necessary to improve the fabrication of poly gate such that these extrusions vanish and the structure of metal silicide layer is stationary during any following treatment of poly gate.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming a poly gate structure is provided. The method substantially improves the problem that structure of metal silicide is varied during the fabrication of poly gate and then the surface of poly gate is roughened by metal silicide extrusion, which induces some disadvantages, for instance the gate to gate short. Furthermore, the provided invention requires no any special process and is feasible to perform with these widespread used processes of semiconductor device fabrication.
In one embodiment, the method is used to form a poly gate structure in a semiconductor substrate. The provided method comprises following steps. First, a dielectric layer is formed over a substrate and then a polysilicon layer is formed over the dielectric layer. Second, a metal silicide layer is formed on the polysilicon layer, and just after it is formed entirely, the metal silicide layer is annealed such that the structure of metal silicide layer is totally phase transformed. Where both the annealing temperature and the annealing time are strongly dependent on the fabrication of poly gate, and are adjusted to let the final annealed structure of metal silicide layer is fixed during any further treatment of poly gate. Afterwards, a passivation layer is formed over the annealed metal silicide layer, and then a photoresist layer is used to define the gate region over the passivation layer. Thus, anisotropically etching process is used to form the primly structure of poly gate. Finally, the photoresist layer is removed, an annealing process is used to repair the etching scars on the surface of poly gate and sidewall oxide is formed on sidewall of poly gate to protect it. The key point of the invention is that after metal silicide layer is formed, an annealing process is used to anneal it before any following fabrication of poly gate. The original structure of metal silicide layer is then transformed to the most stable structure and no phase transformation of metal silicide layer will be occur in following fabrication of poly gate.
In another embodiment according to the present invention, a poly sate structure of a dynamic random access memory (DRAM) is formed by the provided method. The chiefly details of the embodiment are similar to the previous embodiment except some difference. First, the substrate includes a dynamic random access memory and the poly gate is used to provide the gate of metal-oxide-semiconductor of DRAM. Second, the dielectric layer is a silicon oxide layer and the metal silicide layer is a tungsten silicide layer. Third, the annealing process completely changes the structure of tungsten silicide layer from hexagonal structure to tetragonal structure.
REFERENCES:
patent: 5612249 (1997-03-01), Sun et al.
patent: 5672544 (1997-09-01), Pan
patent: 5902125 (1999-05-01), Wu
patent: 5998286 (1999-12-01), Chen et al.
Huang Michael WC
Yew Tri-Rung
Bacon & Thomas PLLC
Dang Phuc T.
Nelms David
United Microelectronics Corp.
LandOfFree
Method for forming a poly gate structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a poly gate structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a poly gate structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2548122