Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-17
2004-09-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S681000
Reexamination Certificate
active
06787461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for forming a plug metal layer, and in particular to a method for forming the plug tungsten (W) layer.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductor devices, become highly integrated the area occupied by the device shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks to the deep sub-micron region, some problems described below are incurred due to the scaling down process.
Generally known in the art of integrated circuit fabrication is the use of titanium nitride layers. Titanium nitride layers within integrated circuit fabrication are most commonly employed as either barrier layers or adhesion promoter layers. When employed as barrier layers, titanium nitride layers are typically formed interposed between a conductor metallization layer and a doped silicon layer or a doped silicon semiconductor substrate. When formed in this location, a titanium nitride layer provides a barrier to inhomogeneous inter-diffusion and spiking from the conductor metallization layer into the doped silicon layer or the doped silicon semiconductor substrate. Titanium nitride layers, which are employed as barrier layers, are particularly well evolved within integrated circuit fabrication. Alternatively, when employed as adhesion promoter layers, titanium nitride layers within integrated circuits are typically formed as liner layers beneath blanket tungsten layers from which in turn are formed conductive contact and interconnection studs through patterned dielectric layers within those integrated circuits.
While the barrier layer characteristics of titanium nitride layers have made titanium nitride layers quite common within integrated circuit fabrication, methods through which such titanium nitride layers may be formed within integrated circuits are not entirely without problems. In particular, within the titanium nitride layers the integrated circuit device dimensions have decreased, and the aspect ratios of apertures has increased within those integrated circuits. It has become increasingly difficult to form, through conventional physical vapor deposition (PVD) sputtering methods, titanium nitride layers with adequate step coverage. The difficulty derives from the inherent line-of-sight deposition characteristics of conventional physical vapor deposition (PVD) sputtering methods employed in forming integrated circuit layers of titanium nitride, as well as other materials. The line-of-sight deposition characteristics typically provide only limited sidewall and bottom coverage of titanium nitride within a narrow high aspect ratio aperture (i.e. an aperture of width less than about 0.5 microns and aspect ratio greater than about 3). Titanium nitride layer which is desired in comparison with titanium nitride coverage upon the surface of the integrated circuit layer (typically a dielectric layer) within which is formed the aperture.
In response to the step coverage limitations inherent in forming titanium nitride layers through physical vapor deposition (PVD) sputtering methods, there has alternatively been proposed and disclosed the use of chemical vapor deposition (CVD) methods for forming titanium nitride layers within integrated circuits. Titanium nitride layers formed through chemical vapor deposition (CVD) methods have inherently superior step coverage within narrow high aspect ratio apertures within integrated circuits since chemical vapor deposition (CVD) methods, in general, proceed through a surface diffusion deposition phenomenon rather than a line-of-sight deposition phenomenon.
Although chemical vapor deposition (CVD) methods may be employed within integrated circuits to provide titanium nitride layers with superior step coverage for narrow high aspect ratio apertures. Chemical vapor deposition (CVD) methods are also not entirely without problems when forming titanium nitride layers within integrated circuits with optimally desirable properties. In that regard, it is difficult to deposit titanium nitride layers at comparatively low temperatures (i.e. less than a temperature of about 550 degrees centigrade at which aluminum containing conductor metallization layers deteriorate) through low pressure chemical vapor deposition (LPCVD) methods. Simultaneously, it is also difficult to deposit titanium nitride layers with a low resistivity and impurity concentration through metal organic chemical vapor deposition (MOCVD) methods. Particularly undesirable impurities formed within titanium nitride layers deposited through metal organic chemical vapor deposition (MOCVD) methods are carbon, oxygen, and hydrogen. These impurities increase the difficulty of the subsequent process, for example, a gap fill process.
In general, a titanium layer and a titanium nitride layer are first formed to form a barrier layer in the process for forming a plug tungsten layer. Next, the titanium nitride layer is treated by way of using a plasma process, and then the tungsten process is performed. Nevertheless, there is the directional issue when the conventional plasma process for the treatment of the barrier layer is used to treat the surface of the barrier layer in the via hole. That is, the treatment of the conventional plasma process can not overall suffuse the barrier layer and, hence, the treatment of the titanium nitride layer on the sidewall of the via hole is incomplete. Furthermore, if the titanium nitride layer is formed by way of metal organic chemical vapor deposition (MOCVD), the titanium nitride layer on the sidewall of the via hole without plasma will have residual volatility solvent therein, therefore causing “out gasing”.
The issues above result from the most commonly used precursors for metal organic chemical vapor deposition (MOCVD) are TDMAT and TDEAT, which might end up with a TiN layer having carbon and/or hydrogen byproducts after a thermal dissociation process. A conventional method used in solving the above problem is by using nitrogen (N
2
) and/or hydrogen (H
2
) plasma treatment to reduce the byproduct content within the TiN layer, as well as reducing its resistivity and water absorption.
Nevertheless, anisotropic plasma treatment against deeper trenches, that is, trenches having high aspect ratios, can not effectively remove the residing byproducts in the sidewalls of the via/contact holes. Thus, the byproduct contents at the sidewall and at the top of the via/contact holes are very different, which result in different metal deposition rates over the treated/untreated TiN barrier layer at later stages, that is, selectivity of the metal chemical vapor deposition. As shown in
FIG. 1
, the selectivity of the metal chemical vapor deposition is a ratio of the thickness of the metal nucleation, wherein the ratio (b/a) is the thickness of the metal nucleation on the top of the via hole (with the treatment of plasma) and the sidewall of the via hole (without the treatment of plasma). In the conventional process for the metal chemical vapor deposition, the ratio of b to a is about 40 to 60% or 50 to 70% that is due to the sidewall of the via hole can not be treated with the plasma process and, hence, uncontinuous and insufficient nucleation sites.
In such, the side-wall deposition rate is less than the top deposition rate, as the plug metal is laid down, it tends to cover the via/contact holes before the metal layer covering the opposite sides of the holes meets. This forms an open area in the holes called a “seam” phenomena. When the plug metal layer etch back is performed, the void is opened, which forms an irregular upper surface on the metal plug in the well. It is very difficult to form a good contact between the irregular upper surface of the open via/contact plug and the interconnect line. Metal applied to such irregular surfaces tends to crack or break over time, such
Chuang Chia-Che
Wang Yu-Piao
Dickinson Wright PLLC
United Microelectronics Corp.
Vu David
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