Method for forming a planarized composite metal layer in a semic

Details Method for forming a planarized composite metal layer in a semic Method for forming a planarized composite metal layer in a semic

1992-01-31

1993-11-30

Quach, T. N.

Fishing, trapping, and vermin destroying

437189, 437190, 437192, 437194, 437197, 437199, H01L 21441

Patent

active

052665216

ABSTRACT:
A method for manufacturing a semiconductor device, comprising the steps of forming an insulating interlayer on a semiconductor substrate to provide a semiconductor intermediate product, providing the insulating interlayer with an opening, forming a first metal layer on the semiconductor intermediate product, heat-treating the first metal layer to fill up the opening with the metal, forming a second metal layer on the first metal layer, and then heat-treating the second layer to planarize the metal layer. An alternative embodiment of the invention encompasses a method for manufacturing a semiconductor device, comprising the steps of providing a semiconductor wafer with an opening formed thereon, forming a metal layer on the semiconductor wafer, and then heat-treating the metal layer to fill up the opening with the metal, wherein pure Al or an aluminum alloy having no Si component is used as the metal in forming the metal layer.

REFERENCES:
patent: 4650696 (1987-03-01), Raby
patent: 4920070 (1990-04-01), Mukai
patent: 4970176 (1990-11-01), Tracy et al.
Wolf, et al., VLSI Processing, Lattice Press, 1986, vol. 1, pp. 331-381.
Pauleau, Y., "Interconnect Materials for VLSI Circuits" Solid State Technology, vol. 30, No. 6 (Jun. 1987), pp. 101-105.

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