Method for forming a passivation layer on copper conductive...

Details Method for forming a passivation layer on copper conductive... Method for forming a passivation layer on copper conductive...

2000-03-31

2002-01-22

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S633000, C438S634000, C438S675000

Reexamination Certificate

active

06340638

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a semiconductor process on copper chips and more particularly, relates to a method for forming a passivation layer on copper conductive elements on a semiconductor chip and devices formed by the method.
BACKGROUND OF THE INVENTION
Copper chips, i.e., semiconductor chips that have copper conductive layer as top metal have been widely used and developed in recent years. One of the most widely used copper applications is the copper interconnect that is formed by either a damascene or a dual damascene process. A typical damascene process and dual damascene process are shown in
FIGS. 1 and 2
, respectively.
In a single damascene process, shown in FIGS.
1
A~
1
E, a via plug
12
of tungsten is first formed after an oxide layer
14
is planarized by a chemical mechanical polishing process. On top of the IC structure
10
is then deposited, by a plasma enhanced chemical vapor deposition process, an inter-layer-dielectric (ILD) layer
16
of silicon oxide. This is shown in FIG.
1
B. Openings
18
for trenches or conductive lines are then patterned by a photoresist layer (not shown) and formed by a reactive ion etching method for metal lines. This is shown in FIG.
1
C. In the next step of the process, as shown in
FIG. 1D
, a conductive metal such as copper is deposited to fill the openings
18
for the trenches or conductive lines. A typical process used for copper deposition can be CVD, electrodeposition or electroless deposition. The copper material
20
covers not only the openings
18
but also on top of the patterned oxide layer
16
.
It should be noted that after the via plug
12
process, the ILD layer
14
is deposited without requiring a planarization since the top surface is already flat. The excess metal
20
on top of the ILD layer
16
is then removed by a chemical mechanical polishing process, resulting in a planar structure of a flat top surface
22
that has metal inlays
20
, i.e., the copper trenches or copper conductive lines, in the ILD layer
16
.
The damascene process provides several processing advantages over the traditional metal/ILD/planarization process. For instance, the surface at any time during the process is totally flat, and the damascene process eliminates the difficulty in filling small gaps between metal lines. Furthermore, the damascene process eliminates the difficultly in metal etching, particularly in hard-to-etch metal such as copper. While damascene process provides numerous benefits, it is more complex and requires a via plug process and a CMP process for both the metal and the ILD layer. Morever, the damascene process requires a flat topography to start out with in order to form subsequent flat surfaces.
A more frequently used process for forming copper conductors in a back-end-of-line (BEOL) process is shown in FIGS.
2
A~
2
C. In the dual damascene process, vias and trenches are defined by using two separate lithographic and reactive ion etching steps. However, the via plug is filled in the same deposition step as the metal line. Dual damascene process reduces the number of processing steps by reducing the barrier layer depositions from two to one and by eliminating the CVD tungsten plug deposition process. A further benefit achieved in the dual damascene process is that the via plug is formed of the same conductive metal as the metal line and thus eliminating the risk of via electromigration failure.
As shown in
FIG. 2A
, the semiconductor structure
30
is built with metal conductive lines
32
formed in an ILD layer
34
which is then planarized to form a flat top surface
36
with a photoresist layer
38
deposited and patterned thereon. Openings
40
are formed by the patterning process to provide locations for next level metal lines to be formed. After the formation of the opening
40
, the photoresist layer
38
is stripped and then a second photoresist layer
42
is applied on top of the IC structure
30
. Via pattern is then defined and a via opening
44
is formed by a reactive ion etching process. This is shown in FIG.
2
B.
In the next step of the dual damascene process, as shown in
FIG. 2C
, a conductive metal such as copper is deposited to fill both the via opening
44
and the trench opening
40
after the second photoresist layer
42
is first removed. The conductive metal deposition process can be carried out by either a CVD process, an electrodeposition process or an electroless deposition process. The novel step for the dual damascene process allows the via
46
and the trench
48
to be formed of the same conductive metal, such as copper. After the metal deposition process, excess metal (not shown) is removed by a CMP process to provide a smooth top surface
50
.
After the copper damascene or dual damascene interconnects are formed, and insulating material layer, i.e., or a passivation layer of a dielectric material must be deposited on top of the IC structure in order to provide electrical insulation. This is shown in FIGS.
3
A~
3
C. As copper trench
20
(or
48
shown in
FIG. 2C
) of
FIG. 1
is used as the top metal conductor by the damascene or dual damascene process, the top surface
50
is planarized into a flat surface, as shown in
FIG. 3A. A
diffusion barrier layer
52
is then deposited on top of the surface
50
to protect copper trench
20
from diffusing into the subsequently deposited passivation layer
54
, as shown in
FIGS. 3B and 3C
. The passivation layer
54
in the copper trench
20
has a wide flat contact which presents an adhesion failure problem, i.e., or a peeling problem. The wider the flat surface, the greater potential it has to cause peeling from the flat structure.
The adhesion between copper and dielectric materials such as silicon oxide, polyimide etc. is poor. While methods have been proposed to improve the adhesion of copper to the dielectric layer, such as by treatment of the interface or by using adhesion-promoting films, none of these methods is effective when a wide flat area between copper and dielectric layer of a passivation material is involved. The passivation layer
54
is normally formed of an undoped silicate glass (USG) or a spin-on-glass (SOG) material. When the adhesion-promoting film layer is used, the film layer must also be a diffusion barrier layer in order to stop diffusion of copper atoms into the dielectric material layer, and thus, only the use of adhesion layers which are also good barriers, can be of any practical value.
In the conventional method of using AlCu metal which contains a small amount of copper as the top metal layer, there is a design rule for assembly stress protection. The design rule is used to avoid passivation layer peeling at a wide flat area. However, when pure copper is used as the top metal layer, there is no design rule that can be used to protect the layer from assembly stress, specifically, at a wide flat area. There is a great potential of passivation layer peeling at such area.
It is therefore an object of the present invention to provide a method for forming a passivation layer on copper conductive elements that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming a passivation layer on copper conductive elements that does not have passivation layer peeling or adhesion failure problem.
It is a further object of the present invention to provide a method for forming a passivation layer on copper conductive elements with improved adhesion between copper and the passivation layer over a wide flat area.
It is another further object of the present invention to provide a method for forming a passivation layer on copper conductive elements after a CMP process by creating a corrugated surface between the copper and the passivation material layer.
It is still another object of the present invention to provide a method for forming a passivation layer on copper conductive elements that does not have the adhesion failure problem by etching a top surface of the semiconductor d

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