Method for forming a notched gate insulator for advanced MIS...

Details Method for forming a notched gate insulator for advanced MIS... Method for forming a notched gate insulator for advanced MIS...

2007-01-02

2007-01-02

Richards, N. Drew (Department: 2815)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ordering or disordering

C438S305000

Reexamination Certificate

active

10966152

ABSTRACT:
Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.

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