Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-09-29
2001-01-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S287000, C438S769000, C438S786000, C438S787000
Reexamination Certificate
active
06177363
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for fabricating integrated circuits and, in particular, a method that includes the introduction of a nitride layer in an ultra-thin gate dielectric for the integrated circuit. The invention also relates to an integrated circuit that includes the inventive nitride layer.
BACKGROUND OF THE INVENTION
Recent advances in the field of metal-oxide-semiconductor (“MOS”) technology have included scaling down of gate dielectric thickness. As the thickness of these devices decreases, a number of problems have been encountered. For example, as the overall size becomes “ultra-thin”, e.g., less than 75 Å, the quality of the Si/SiO
2
interface characteristics play dominate roles in determining the quality of gate oxide. In fact, film thicknesses below 25 Å suffer from excessive tunneling current (>1A/cm
2
) problems as they approach the tunneling limit. On such thin gate dielectrics, suppression of boron diffusion from p
+
poly gate into channel regions is also a serious concern. These problems have severely hampered the ability to fabricate integrated circuit utilizing “ultra-thin” designs.
To address such problems, the art has sought to provide a reliable, high quality gate dielectric having the desired properties of low defect density, D
o
, and high breakdown field strength, F
bd
, that retains its quality during advanced processing. Although the art has been able to provide oxide
itride (ON) and oxide
itride/oxide (ONO) structures having excellent (lower D
o
) behavior, such structures have suffered from serious charge trapping problems. That is, because the oxidizing species will not penetrate the nitride layer, the interface (nitride/oxide) traps cannot be annealed. Thus, nitride structures cannot be effectively employed on gate dielectrics.
Stacked oxides, however, have alleviated such problems, thereby achieving simultaneous solutions to low leakage (low D
o
) and low trap densities (D
it
,Q
f
).
For example, U.S. Pat. No. 4,851,370 includes a composite stack synthesized by a three-step grow-deposit-grow technique where the growing steps are conducted at pressures equal to or greater than one atm to achieve ultra-low D
o
, D
it
oxides with a planar and stress free Si/SiO
2
. This patent is incorporated by reference in its entirety for all purposes.
Alternatively, a copending U.S. application of the same assignee, i.e., U.S. Application Serial No. (Brady Apr. 10, 1935) which is incorporated herein by reference, discloses certain low pressure techniques for providing a stacked oxide arrangement for thinner gate dielectrics, e.g., less than 65 Å. This method can also involve a sequence of grow-deposit-grow steps, however, in this case, the steps are performed in a zone of low pressure, e.g., a pressure that is preferably about 200 milliTorr to 950 milliTorr. The use of such low pressures can, e.g., retard the oxidation rate at which the first and second oxide layers are grown.
The resulting stack structure has superior electrical and substructural properties as compared to that provided by a conventional oxidation scheme. The method disclosed in this copending application also allows the ultra-thin oxide layers to be formed in a single furnace cluster step that can significantly decrease the cost of the process.
Despite the significant advantages that can be associated with these stacked oxide arrangements, they have not effectively resolved boron (B) diffusion issues.
Thus, the need still exists for a gate dielectric which is capable of providing both the advantages associated with the stacked oxides, e.g., a low interfacial trap, and which is also a suitable boron blocker.
SUMMARY OF THE INVENTION
The present invention is based at least in part on the surprising discovery that a controlled quantity of defects can be introduced into a nitride layer and that these defects are capable of significantly minimizing (or even eliminating) the charge trap problem that has prevented the use of nitride containing structures on gate dielectrics.
A first aspect of the invention relates to a method for forming a nitride layer in which defects are introduced into the nitride layer. In particular, the method provides a defect density for nitride layer that is sufficiently large for diffusional transport of one or more annealing species, e.g., O
2
N
2
,H
2
,N
2
O, and the like, to reduce the interfacial trap density. To this end, the nitride layer is preferably introduced onto the oxide layer under conditions of both low temperature, e.g., less than 900 C and low pressure, e.g., of less than 1 Torr.
Another aspect of the invention relates to a method for forming an ON gate dielectric which can be employed in an ultra-thin integrated circuit environment. This method comprises the steps of providing an oxide layer either directly or indirectly on a semiconductor substrate and then depositing a nitride layer on the oxide layer under conditions effective to introduce defects into the nitride layer. Here, the nitride layer includes an amount of defects sufficiently large to be semi-transperent to oxygen diffusion so as to allow annealing out of the interfacial traps. This method can further include the additional introduction of the second oxide layer on the nitride layer to provide an ONO structure.
Yet another aspect of the invention involving the use of low pressure oxidation that allows for the controlled formation of the oxide as well as nitride layer and thus, provide an ultra-thin gate dielectric.
In another aspect of the invention, each of the oxide layers as well as the nitride layer is performed in a single furnace cluster.
Other aspects of the invention relate to the gate dielectric as well as an integrated circuit utilizing the gate dielectric. These and other aspects of the invention will become apparent from the description and claims that follow.
REFERENCES:
patent: 4623912 (1986-11-01), Chang et al.
patent: 4814291 (1989-03-01), Kim et al.
patent: 4851370 (1989-07-01), Doklan et al.
patent: 5132244 (1992-07-01), Roy
patent: 5153701 (1992-10-01), Roy
patent: 5536667 (1996-07-01), Cho
patent: 5940736 (1999-08-01), Brady et al.
P.K. Roy, D. Brady, S. Chetlur, Y. Ma & K. Morse, “Synthesis of Ultra-Thin Stacked Oxides Using Low Pressure Single Furnace Cluster Process”,Mat. Res. Socl Symp. Proc., 1977 Materials Research Society, pp. 89-94.
P.K. Roy and I.C. Kizily Alli, Stacked High-Dielectric Constant Gate Dielectric for Gigascale Integration of Metal-Oxide-Semiconductor Technologies:,Applied Physics Letters, Jun. 1, 1998, vol. 72, No. 22, pp. 2835-2837.
Laughery Michael A.
Ma Yi
Roy Pradip K.
Ghyka Alexander G.
Lucent Technologies - Inc.
Niebling John F.
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