Method for forming a multilevel interconnect

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S627000

Reexamination Certificate

active

06306757

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a multilevel interconnect.
2. Description of the Prior Art
The conventional method for forming a multilevel interconnect is illustrated below. A metal
04
is firstly provided, on which there is an intermetal dielectric (IMD)
05
layer; a via is then formed. A first Ti/TiN layer, which is a couple of titanium nitride (TiN) film and underlying titanium (Ti) film, is formed on the IMD and all surfaces in the via. Therein, the portion located on IMD serves as a glue layer, and the other as a barrier layer
06
. Next, a tungsten (W) layer
03
is formed on the Ti/TiN layer and planarized by chemical mechanical polishing (CMP) process. Therefore, the glue, which was located on IMD, is removed. The following process is sputtering a second Ti/TiN layer on the IMD and the residual tungsten plug. Surely, the second Ti/TiN layer serves as a glue layer, and a metal such as aluminum (Al) is then formed on it. The following procedures are used to define the metal. A photoresist is formed on the metal, then a mask and an exposure process are used to pattern the photoresist. After stripping the unnecessary portion of the photoresist, the metal is etched. Subsequently, the residual photoresist is stripped and the resultant is as shown in FIG.
1
.
As described above, the conventional glue layer scheme employs thin sputtered layer of Ti
01
/TiN
02
stack after W-CMP in order to recover the glue layer consumed by W-CMP. However, when unlanded via rule is used, this scheme suffered from Ti errosion problem. The electrochemical reaction between Ti
01
/solvent/W
03
will erode the Ti
01
film and result in high via resistivity.
For the foregoing reason, there is a need for a method for forming a multilevel interconnect, which can prevent the occurrence of high via resistivity from stripping the photoresist.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming the multilevel interconnect that substantially solves the problem of high via resistivity. In one embodiment, a conductor layer on which a dielectric layer is provided firstly. A first Ti/TiN layer is formed on the dielectric layer. Next, an opening, such as a via or a contact hole, is formed. A second Ti/TiN layer is formed on the first Ti/TiN layer and all surfaces in the opening. Its followed by forming a tungsten (W) on the second Ti/TiN layer to fill the opening. Chemical mechanical polishing (CMP) is used to polish the tungsten and the second Ti/TiN layer until the first Ti/TiN layer exposes. Lastly, a metal layer is defined on the first Ti/TiN layer, therein the metal layer contacts with tungsten.


REFERENCES:
patent: 5407861 (1995-04-01), Marangon et al.
patent: 5955785 (1999-09-01), Gardner et al.
patent: 5981385 (1999-11-01), Huang

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