Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-04-22
2002-12-31
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S778000, C438S781000
Reexamination Certificate
active
06500770
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor device manufacturing methods and more particularly to methods for forming a multi-layer protective coating including a plurality of protective sealing layers over low-k (dielectric constant) porous insulating material to prevent migration of chemical species including water (H
2
O).
BACKGROUND OF THE INVENTION
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic capacitive effects of insulating materials in which metal interconnects are formed to interconnect devices. It has become necessary to reduce capacitance of the insulating layers to allow the insulating layer thicknesses to shrink along with other device features such as metal interconnect line width. As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials.
Manufacturing processes such as, for example, damascene processes, have been implemented to form metallization vias and interconnect lines (trench lines) by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple layers of metallization vias and interconnect lines (trench lines). For example, in the dual damascene process, a trench opening and via opening is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a substrate including another conductive area over which the vias and trench lines are formed and in communication with. After a series of photolithographic steps defining via openings and trench openings, via and the trench openings are filled with a metal, preferably copper, to form metallization vias and interconnect lines (trench lines), respectively. The excess metal above the trench line level is then removed by well known chemical-mechanical planarization (polishing) (CMP) processes.
As indicated, advances in semiconductor device processing technology demands the increasing use of low-k (low dielectric constant) insulating materials in, for example, IMD (ILD) layers that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials has become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants less than about 3.0 for achieving integration of, for example, 0.13 micron interconnections. In the future, even lower dielectric constant material, for example less than about 2.5, will be required for 0.1 micron process integration, and dielectric constants of less than about 2.0 will be required for 0.07 micron process integration.
One exemplary low-k inorganic material that is frequently used, for example, is carbon doped silicon dioxide (C-oxide) formed by a CVD process where the dielectric constant may be varied over a range depending on the process conditions. C-oxide, for example, may be formed with dielectric constants over a range of about 2.0 to about 3.0 and density of about 1.3 g/cm
3
compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm
3
for silicon dioxides (e.g., un-doped TEOS). Other exemplary low-k inorganic materials include porous oxides, xerogels, or SOG (spin-on glass). Exemplary low-k organic materials include polysilsequioxane, parylene, polyimide, benzocyclobutene and amorphous Teflon.
Low-k materials believed to be required to achieve integration of 0.07 micron devices will require low-k materials (ultra low-k) with a dielectric constant of less than about 2.0. Such low-k materials will typically require a porosity of 50 per cent to 80 percent by volume. An exemplary class of materials able to achieve this level of porosity includes porous silica films. Porous silica films are generally formed with a porosity of about 20% or greater and with pore sizes that range from about 1 nm to about 100 nm. The density of the silicon containing composition, including the pores, ranges from about 0.1 to about 1.9 g/cm
3
. Yet another material that has received recent attention for use as an ultra low-k material in semiconductor devices are mesoporous silicates, such as molecular sieve materials, that have a well determined pore structure with a narrow size distribution, such as a honeycomb structure including repeating units of cage-like pores. Examples of molecular sieves having, for example, a channel-typed micropore structure include TSM and silicalate. Mesoporous materials have a pore size from about 10 to about 500 Angstroms. These materials may have porosities from about 50 percent to about 80 percent and can have dielectric constants of less than about 2.0. One advantage of these materials is their relatively high strength due to their crystalline nature. Yet another class of ultra low-k materials includes aerogels. Aerogels are generally created by acid catalyzed hydrolysis of precursors such as tetraethylorthosilicate (TEOS) and tetramethylorthosilicate (TMOS) under controlled atmosphere conditions including and aging and drying period.
As might be expected, the development of porous low-k materials has presented several problems in manufacturing methods that must be overcome such as material strength and tendency to absorb chemical species such as water. One important limitation of porous low-k materials is low strength tendency to crack or peel in subsequent manufacturing processes including, for example, chemical mechanical planarization (CMP). In order to protect the porous low-k insulating material layers, it has been necessary to add a capping layer over the porous low-k insulating layer including for example, silicon nitride (SiN) and silicon oxynitride (SiON). Additionally, silicon carbide (SiC) has been used as a capping layer to protect the insulating layer in subsequent processing steps including CMP.
One problem with the prior art capping layer technology is that due to the high porosity present in low-k insulating materials, is that adhesion of the capping layers of the prior art is poor and undesirably add to the overall dielectric constant of the multi-layer device. For example, SiC has a dielectric constant of about 5.0 and the metal nitrides such as SiN and SiON have dielectric constants greater than 5.0. Capping layers are necessary, however, to protect the increasingly porous low-k materials have proven necessary to both protect the low-k material during subsequent processing steps including CMP, and to prevent the porous low-k material from absorbing moisture.
Many of the porous low-k and ultra low-k materials including mesoporous and nanoporous structures include an interconnecting pore structure that allows chemical species, such as water (H
2
O), to readily migrate through the low-k material presenting serious problems in subsequent processing steps. Thus, for example, during an RIE etching step in an oxygen containing plasma to remove the photoresist used to pattern via openings or trench openings, the low-k material produces hydrophilic bonds and absorbs moisture. During subsequent metal deposition to fill via holes and trench openings to form metal interconnects, outgassing of the moisture occurs, causing oxidation of metal contacts resulting in via poisoning, or high resistivity of the via interconnect due to the oxidized metal contacts or interconnects. A further problem with water absorption on hydroph
Cheng Yu-Huei
Yu Chen-Hua
Ghyka Alexander
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
LandOfFree
Method for forming a multi-layer protective coating over... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a multi-layer protective coating over..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a multi-layer protective coating over... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2992035