Method for forming a line-on-line multi-level metal interconnect

Details Method for forming a line-on-line multi-level metal interconnect Method for forming a line-on-line multi-level metal interconnect

1998-03-13

1999-08-10

Dang, Trung

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438618, 438626, 438630, 438633, 438637, 438645, 438675, 438685, 438648, 438649, 438620, H01L 21768

Patent

active

059373245

ABSTRACT:
A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).

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patent: 5374592 (1994-12-01), MacNaughton et al.
patent: 5510294 (1996-04-01), Dixit et al.

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