Method for forming a high voltage gate dielectric for use in int

Details Method for forming a high voltage gate dielectric for use in int Method for forming a high voltage gate dielectric for use in int

1997-07-03

1999-01-19

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438787, 438788, 438773, 438981, 438257, 438263, 438264, 438267, 438211, 438216, 438119, 438593, 148DIG117, 148DIG163, H01L 2170

Patent

active

058613471

ABSTRACT:
A method for form an integrated circuit device begins by growing a tunnel oxide (22). The tunnel oxide is exposed to a nitrogen containing ambient whereby nitrogen is incorporated at atomic locations at the interface between the tunnel oxide (22) and a substrate (11). This tunnel oxide and nitrogen exposure is performed for all of a floating gate active area (12), a high voltage active area (14) and a logic gate active area (16). A floating gate electrode (24) and interpoly dielectric regions (26 through 30) are then formed in the floating gate region (12). The tunnel oxide (22) is etched from the active areas (14 and 16) whereby nitrogen contamination (32) may remain. An optional sacrificial oxidation and a low temperature 830.degree. C. wet oxidation process utilizing HCL, H2 and O2 is then used to grow a high voltage gate dielectric (34) which has been shown to improve charge to breakdown characteristics by a factor of 1,000. After the formation of the high voltage gate oxide (34), a lower voltage logic gate oxide (36) is then formed.

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