Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-17
2002-01-01
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000
Reexamination Certificate
active
06335274
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a fabrication method of integrated circuits, and more particularly to a high-reflectivity index (RI) oxide film to reduce fluorine substances out diffusion from High Density Plasma enhanced Chemical Vapor Deposition (HDP-CVD) Fluorinated Silicate Glass (FSG).
2. Description of the Prior Art
In the fabrication of microelectronic semiconductor devices on a wafer substrate, such as silicon, to form an integrated circuit, various metal layers and insulation layers are deposited thereon in selective sequence. The insulation layers, e.g., of silicon dioxide, silicon oxynitride (SiO
x
N
y
), fluorinated silicate glass (FSG), also called fluorinated silicon oxide, spin-on glass (SOG), etc., serve as electrical insulation between metal layers, e.g., intermetal dielectric (IMD) layers, as protective layers, as gap filling layers to achieve planarization (layer flatness) in the wafer substrate, and the like, as the case may be. The individual layers are deposited by conventional technique such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD, etc.
Fluorinated silicate glass (FSG) is one of the favorable low dielectric materials used for intermetal dielectric (IMD) in connection with metallization techniques before so-called back end of the line operations. To deposit FSG, for example, either high density plasma enhanced chemical vapor deposition (HPD-CVD) is used extensively.
The dielectric constant achievable for FSG is about 3.3 depending on the fluorine concentration in the FSG film and the precursor used to deposit the FSG film. A higher fluorine concentration usually provides a lower dielectric constant. However, a higher fluorine concentration makes the film unstable because free fluorine tends to diffuse or migrate out of the film to adjacent layers in the IC.
Out diffusion of fluorine substances (including fluorine itself and attendant self-generating contaminant compounds thereof with other contaminating precursor constituents) from FSG can create bubbles that collect at interfaces with metal layers, resulting in metal peeling problems due to corrosion or poisoning, and the like. In many cases, the use of FSG is combined with post plasma treatment, e.g., plasma treatment using oxygen and nitrogen or nitrous oxide (N
2
O), or the inclusion of a silicon dioxide cap layer to minimize fluorine substances out diffusion. However, fluorine substances, including fluorine itself, will diffuse well into silicon dioxide films and the diffusion length (penetration depth) thereof can be in excess of several thousand angstroms.
It is desirable to have an arrangement of FSG as an IMD layer in a semiconductor device in which out diffusion of fluorine substances is prevented so as to avoid metal peeling problems, especially if this is attained essentially without increasing the manufacturing costs.
SUMMARY OF THE INVENTION
It is an object of the invention that a high-RI silicon dioxide dielectric liner layer can reduce out diffusion of fluorine substances in FSG layer.
In accordance with the present invention, a method is provided comprising following steps. First, a conductive layer is deposited on a substrate, wherein the conductive layer is patterned on the substrate. Then, a dielectric liner layer is formed by high density plasma enhanced chemical vapor deposition method or plasma enhanced chemical vapor deposition method on the substrate and the conductive layer. The dielectric liner is silicon dioxide and has a high-RI between about 1.5 to 1.8. Next, a fluorinated silicate glass layer is deposited on the dielectric liner layer. The high-RI dielectric liner layer is used to reduce out diffusion of fluorine substances in the fluorinated silicate glass layer. Last, it is proceeded a chemical mechanism polishing process to remove additional fluorinated silicate glass layer and the dielectric liner layer.
REFERENCES:
patent: 6008120 (1999-12-01), Lee
patent: 6149987 (2000-11-01), Perng et al.
patent: 6217658 (2001-04-01), Orezyl et al.
Jeng Pei-Ren
Wu Shu-Li
Le Thao P.
Macronix International Co. Ltd.
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