Method for forming a high quality ultrathin gate oxide layer

Details Method for forming a high quality ultrathin gate oxide layer Method for forming a high quality ultrathin gate oxide layer

1997-03-11

1999-08-17

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438787, 438790, 438770, 438762, H01L 2102

Patent

active

059407360

ABSTRACT:
This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface to with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (<5%) for certain devices, often required due to improved resistance to boron and other dopant diffusion and hot-carrier characteristics, N.sub.2 O or NO in the oxidant are used during each steps of the stacked oxide synthesis. Planar and stress-reduced Si/SiO.sub.2 interface characteristics is a unique signature of stacked oxide that improves robustness of the gate oxide to ULSI processing resulting in reduced scatter in device parameters (e.g., threshold voltage transconductance), mobility degradation and resistance to hot-carrier and Fowler-Nordheim stress.

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Article from the AT&T Technical Journal; Nov./Dec. 1988 entitled "Synthesis of High-Quality Ultra-Thin Gate Oxides for ULSI Applications" by Pradip K. Roy and Ashok K. Sinha; pp. 155-174.
Article from Semiconductor International; Jul. 1992 entitled "A Robust Gate Dielectric for Submicron Technology" by Hsing-Huang Tseng and Philip J. Tobin; pp. 68-74.
Silicon Processing for the VLSI Era, vol. 1, Wolf et al, pp. 209-210, 1986.

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